1/*
2 * Copyright (c) 2020 Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h7/stm32h7_dualcore.dtsi>
8#include <zephyr/dt-bindings/display/panel.h>
9
10/ {
11	soc {
12		compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
13
14		flash-controller@52002000 {
15			flash0: flash@8000000 {
16				compatible = "st,stm32-nv-flash", "soc-nv-flash";
17				write-block-size = <32>;
18				erase-block-size = <DT_SIZE_K(128)>;
19				/* maximum erase time for a 128K sector */
20				max-erase-time = <4000>;
21			};
22			flash1: flash@8100000 {
23				compatible = "st,stm32-nv-flash", "soc-nv-flash";
24				write-block-size = <32>;
25				erase-block-size = <DT_SIZE_K(128)>;
26				/* maximum erase time for a 128K sector */
27				max-erase-time = <4000>;
28			};
29		};
30
31		dmamux1: dmamux@40020800 {
32			dma-requests= <107>;
33		};
34
35		dmamux2: dmamux@58025800 {
36			dma-requests= <107>;
37		};
38
39		ltdc: display-controller@50001000 {
40			compatible = "st,stm32-ltdc";
41			reg = <0x50001000 0x200>;
42			interrupts = <88 0>, <89 0>;
43			interrupt-names = "ltdc", "ltdc_er";
44			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
45			resets = <&rctl STM32_RESET(APB3, 4U)>;
46			status = "disabled";
47		};
48
49		usbotg_hs: usb@40040000 {
50			compatible = "st,stm32-otghs";
51			reg = <0x40040000 0x40000>;
52			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
53			interrupt-names = "ep1_out", "ep1_in", "wkup", "otghs";
54			num-bidir-endpoints = <9>;
55			ram-size = <4096>;
56			maximum-speed = "full-speed";
57			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
58				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
59			phys = <&otghs_fs_phy>;
60			status = "disabled";
61		};
62
63		usbotg_fs: usb@40080000 {
64			compatible = "st,stm32-otgfs";
65			reg = <0x40080000 0x40000>;
66			interrupts = <98 0>, <99 0>, <100 0>, <101 0>;
67			interrupt-names = "ep1_out", "ep1_in", "wkup", "otgfs";
68			num-bidir-endpoints = <9>;
69			ram-size = <4096>;
70			maximum-speed = "full-speed";
71			clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
72				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
73			phys = <&otghs_fs_phy>;
74			status = "disabled";
75		};
76
77		rtc@58004000 {
78			bbram: backup_regs {
79				compatible = "st,stm32-bbram";
80				st,backup-regs = <32>;
81				status = "disabled";
82			};
83		};
84	};
85	/*
86	* The RAM memories placed here can be used by both cores M4/M7
87	* For more information see reference manual and datasheet to STM32H745
88	* (RM0399 Rev 3)
89	*/
90
91	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
92	sram0: memory@24000000 {
93		reg = <0x24000000 DT_SIZE_K(512)>;
94		compatible = "mmio-sram";
95	};
96
97	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
98	sram1: memory@30000000 {
99		reg = <0x30000000 DT_SIZE_K(128)>;
100		compatible = "zephyr,memory-region", "mmio-sram";
101		zephyr,memory-region = "SRAM1";
102	};
103
104	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
105	sram2: memory@30020000 {
106		compatible = "zephyr,memory-region", "mmio-sram";
107		reg = <0x30020000 DT_SIZE_K(128)>;
108		zephyr,memory-region = "SRAM2";
109	};
110
111	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
112	sram3: memory@30040000 {
113		compatible = "zephyr,memory-region", "mmio-sram";
114		reg = <0x30040000 DT_SIZE_K(32)>;
115		zephyr,memory-region = "SRAM3";
116	};
117
118	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
119	sram4: memory@38000000 {
120		reg = <0x38000000 DT_SIZE_K(64)>;
121		compatible = "zephyr,memory-region", "mmio-sram";
122		zephyr,memory-region = "SRAM4";
123	};
124
125	otghs_fs_phy: otghs_fs_phy {
126		compatible = "usb-nop-xceiv";
127		#phy-cells = <0>;
128	};
129
130	vref: vref {
131		io-channels = <&adc3 19>;
132	};
133
134	vbat: vbat {
135		io-channels = <&adc3 17>;
136	};
137};
138