Lines Matching +full:num +full:- +full:channels
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32e50x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e50x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 clock-frequency = <DT_FREQ_M(180)>;
31 compatible = "mmio-sram";
34 rcu: reset-clock-controller@40021000 {
35 compatible = "gd,gd32-rcu";
39 cctl: clock-controller {
40 compatible = "gd,gd32-cctl";
41 #clock-cells = <1>;
45 rctl: reset-controller {
46 compatible = "gd,gd32-rctl";
47 #reset-cells = <1>;
52 fmc: flash-controller@40022000 {
53 compatible = "gd,gd32-flash-controller";
56 #address-cells = <1>;
57 #size-cells = <1>;
60 compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
61 write-block-size = <2>;
69 max-erase-time-ms = <2400>;
70 page-size = <DT_SIZE_K(8)>;
75 compatible = "arm,armv8m-mpu";
80 compatible = "gd,gd32-usart";
89 compatible = "gd,gd32-usart";
98 compatible = "gd,gd32-usart";
107 compatible = "gd,gd32-usart";
116 compatible = "gd,gd32-usart";
125 compatible = "gd,gd32-usart";
128 interrupt-names = "global", "wkup";
135 compatible = "gd,gd32-dac";
139 num-channels = <2>;
141 #io-channel-cells = <1>;
145 compatible = "gd,gd32-i2c";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 clock-frequency = <I2C_BITRATE_STANDARD>;
151 interrupt-names = "event", "error";
158 compatible = "gd,gd32-i2c";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 clock-frequency = <I2C_BITRATE_STANDARD>;
164 interrupt-names = "event", "error";
171 compatible = "gd,gd32-i2c";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-frequency = <I2C_BITRATE_STANDARD>;
177 interrupt-names = "event", "error";
183 exti: interrupt-controller@40010400 {
184 compatible = "gd,gd32-exti";
185 interrupt-controller;
186 #interrupt-cells = <1>;
188 num-lines = <22>;
191 interrupt-names = "line0", "line1", "line2", "line3",
192 "line4", "line5-9", "line10-15";
197 compatible = "gd,gd32-afio";
204 compatible = "gd,gd32-fwdgt";
210 compatible = "gd,gd32-wwdgt";
218 pinctrl: pin-controller@40010800 {
219 compatible = "gd,gd32-pinctrl-afio";
221 #address-cells = <1>;
222 #size-cells = <1>;
226 compatible = "gd,gd32-gpio";
227 gpio-controller;
228 #gpio-cells = <2>;
236 compatible = "gd,gd32-gpio";
237 gpio-controller;
238 #gpio-cells = <2>;
246 compatible = "gd,gd32-gpio";
247 gpio-controller;
248 #gpio-cells = <2>;
256 compatible = "gd,gd32-gpio";
257 gpio-controller;
258 #gpio-cells = <2>;
266 compatible = "gd,gd32-gpio";
267 gpio-controller;
268 #gpio-cells = <2>;
276 compatible = "gd,gd32-gpio";
277 gpio-controller;
278 #gpio-cells = <2>;
286 compatible = "gd,gd32-gpio";
287 gpio-controller;
288 #gpio-cells = <2>;
297 compatible = "gd,gd32-timer";
300 interrupt-names = "brk", "up", "trgcom", "cc";
303 is-advanced;
304 channels = <4>;
308 compatible = "gd,gd32-pwm";
310 #pwm-cells = <3>;
315 compatible = "gd,gd32-timer";
318 interrupt-names = "global";
321 is-32bit;
322 channels = <4>;
326 compatible = "gd,gd32-pwm";
328 #pwm-cells = <3>;
333 compatible = "gd,gd32-timer";
336 interrupt-names = "global";
339 channels = <4>;
343 compatible = "gd,gd32-pwm";
345 #pwm-cells = <3>;
350 compatible = "gd,gd32-timer";
353 interrupt-names = "global";
356 channels = <4>;
360 compatible = "gd,gd32-pwm";
362 #pwm-cells = <3>;
367 compatible = "gd,gd32-timer";
370 interrupt-names = "global";
373 is-32bit;
374 channels = <4>;
378 compatible = "gd,gd32-pwm";
380 #pwm-cells = <3>;
385 compatible = "gd,gd32-timer";
388 interrupt-names = "global";
391 channels = <0>;
396 compatible = "gd,gd32-timer";
399 interrupt-names = "global";
402 channels = <0>;
407 compatible = "gd,gd32-dma";
412 dma-channels = <7>;
414 #dma-cells = <2>;
419 compatible = "gd,gd32-dma";
424 dma-channels = <5>;
426 #dma-cells = <2>;
433 arm,num-irq-priority-bits = <4>;