Lines Matching +full:num +full:- +full:channels
5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32f403.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
23 clock-frequency = <DT_FREQ_M(168)>;
25 #address-cells = <1>;
26 #size-cells = <1>;
29 compatible = "arm,armv7m-mpu";
37 compatible = "mmio-sram";
40 rcu: reset-clock-controller@40021000 {
41 compatible = "gd,gd32-rcu";
45 cctl: clock-controller {
46 compatible = "gd,gd32-cctl";
47 #clock-cells = <1>;
51 rctl: reset-controller {
52 compatible = "gd,gd32-rctl";
53 #reset-cells = <1>;
58 fmc: flash-controller@40022000 {
59 compatible = "gd,gd32-flash-controller";
61 #address-cells = <1>;
62 #size-cells = <1>;
65 compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
66 write-block-size = <2>;
67 max-erase-time-ms = <300>;
68 bank0-page-size = <DT_SIZE_K(2)>;
69 bank1-page-size = <DT_SIZE_K(4)>;
74 compatible = "gd,gd32-usart";
83 compatible = "gd,gd32-usart";
92 compatible = "gd,gd32-usart";
101 compatible = "gd,gd32-usart";
110 compatible = "gd,gd32-usart";
119 compatible = "gd,gd32-spi";
125 #address-cells = <1>;
126 #size-cells = <0>;
130 compatible = "gd,gd32-spi";
136 #address-cells = <1>;
137 #size-cells = <0>;
141 compatible = "gd,gd32-spi";
147 #address-cells = <1>;
148 #size-cells = <0>;
152 compatible = "gd,gd32-adc";
157 channels = <16>;
159 #io-channel-cells = <1>;
163 compatible = "gd,gd32-adc";
168 channels = <16>;
170 #io-channel-cells = <1>;
174 compatible = "gd,gd32-adc";
179 channels = <16>;
181 #io-channel-cells = <1>;
184 exti: interrupt-controller@40010400 {
185 compatible = "gd,gd32-exti";
186 interrupt-controller;
187 #interrupt-cells = <1>;
189 num-lines = <19>;
192 interrupt-names = "line0", "line1", "line2",
193 "line3", "line4", "line5-9",
194 "line10-15";
199 compatible = "gd,gd32-afio";
206 compatible = "gd,gd32-fwdgt";
212 compatible = "gd,gd32-wwdgt";
220 pinctrl: pin-controller@40010800 {
221 compatible = "gd,gd32-pinctrl-afio";
223 #address-cells = <1>;
224 #size-cells = <1>;
228 compatible = "gd,gd32-gpio";
229 gpio-controller;
230 #gpio-cells = <2>;
238 compatible = "gd,gd32-gpio";
239 gpio-controller;
240 #gpio-cells = <2>;
248 compatible = "gd,gd32-gpio";
249 gpio-controller;
250 #gpio-cells = <2>;
258 compatible = "gd,gd32-gpio";
259 gpio-controller;
260 #gpio-cells = <2>;
268 compatible = "gd,gd32-gpio";
269 gpio-controller;
270 #gpio-cells = <2>;
278 compatible = "gd,gd32-gpio";
279 gpio-controller;
280 #gpio-cells = <2>;
288 compatible = "gd,gd32-gpio";
289 gpio-controller;
290 #gpio-cells = <2>;
299 compatible = "gd,gd32-timer";
302 interrupt-names = "brk", "up", "trgcom", "cc";
305 is-advanced;
306 channels = <4>;
310 compatible = "gd,gd32-pwm";
312 #pwm-cells = <3>;
317 compatible = "gd,gd32-timer";
320 interrupt-names = "global";
323 channels = <4>;
327 compatible = "gd,gd32-pwm";
329 #pwm-cells = <3>;
334 compatible = "gd,gd32-timer";
337 interrupt-names = "global";
340 channels = <4>;
344 compatible = "gd,gd32-pwm";
346 #pwm-cells = <3>;
351 compatible = "gd,gd32-timer";
354 interrupt-names = "global";
357 channels = <0>;
362 compatible = "gd,gd32-timer";
365 interrupt-names = "global";
368 channels = <0>;
373 compatible = "gd,gd32-timer";
376 interrupt-names = "brk", "up", "trgcom", "cc";
379 is-advanced;
380 channels = <4>;
384 compatible = "gd,gd32-pwm";
386 #pwm-cells = <3>;
391 compatible = "gd,gd32-timer";
394 interrupt-names = "global";
397 channels = <2>;
401 compatible = "gd,gd32-pwm";
403 #pwm-cells = <3>;
408 compatible = "gd,gd32-timer";
411 interrupt-names = "global";
414 channels = <1>;
418 compatible = "gd,gd32-pwm";
420 #pwm-cells = <3>;
425 compatible = "gd,gd32-timer";
428 interrupt-names = "global";
431 channels = <1>;
435 compatible = "gd,gd32-pwm";
437 #pwm-cells = <3>;
442 compatible = "gd,gd32-timer";
445 interrupt-names = "global";
448 channels = <2>;
452 compatible = "gd,gd32-pwm";
454 #pwm-cells = <3>;
459 compatible = "gd,gd32-timer";
462 interrupt-names = "global";
465 channels = <1>;
469 compatible = "gd,gd32-pwm";
471 #pwm-cells = <3>;
476 compatible = "gd,gd32-timer";
479 interrupt-names = "global";
482 channels = <1>;
486 compatible = "gd,gd32-pwm";
488 #pwm-cells = <3>;
493 compatible = "gd,gd32-dma";
498 dma-channels = <7>;
500 #dma-cells = <2>;
505 compatible = "gd,gd32-dma";
510 dma-channels = <5>;
512 #dma-cells = <2>;
519 arm,num-irq-priority-bits = <4>;