Lines Matching +full:num +full:- +full:channels
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/timer/nuclei-systimer.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32vf103.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 clock-frequency = <DT_FREQ_M(108)>;
33 compatible = "mmio-sram";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 interrupt-parent = <&eclic>;
47 clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
50 eclic: interrupt-controller@d2000000 {
52 #address-cells = <0>;
53 #interrupt-cells = <2>;
54 interrupt-controller;
61 rcu: reset-clock-controller@40021000 {
62 compatible = "gd,gd32-rcu";
66 cctl: clock-controller {
67 compatible = "gd,gd32-cctl";
68 #clock-cells = <1>;
72 rctl: reset-controller {
73 compatible = "gd,gd32-rctl";
74 #reset-cells = <1>;
79 fmc: flash-controller@40022000 {
80 compatible = "gd,gd32-flash-controller";
82 #address-cells = <1>;
83 #size-cells = <1>;
86 compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
87 write-block-size = <2>;
88 max-erase-time-ms = <300>;
89 page-size = <DT_SIZE_K(1)>;
94 compatible = "gd,gd32-usart";
103 compatible = "gd,gd32-usart";
112 compatible = "gd,gd32-usart";
121 compatible = "gd,gd32-usart";
130 compatible = "gd,gd32-usart";
139 compatible = "gd,gd32-adc";
144 channels = <16>;
146 #io-channel-cells = <1>;
150 compatible = "gd,gd32-adc";
155 channels = <16>;
157 #io-channel-cells = <1>;
161 compatible = "gd,gd32-dac";
165 num-channels = <2>;
167 #io-channel-cells = <1>;
171 compatible = "gd,gd32-i2c";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-frequency = <I2C_BITRATE_STANDARD>;
177 interrupt-names = "event", "error";
184 compatible = "gd,gd32-spi";
190 #address-cells = <1>;
191 #size-cells = <0>;
195 compatible = "gd,gd32-spi";
201 #address-cells = <1>;
202 #size-cells = <0>;
206 compatible = "gd,gd32-afio";
212 exti: interrupt-controller@40010400 {
213 compatible = "gd,gd32-exti";
214 #address-cells = <0>;
215 interrupt-controller;
216 #interrupt-cells = <1>;
218 num-lines = <19>;
221 interrupt-names = "line0", "line1", "line2", "line3",
222 "line4", "line5-9", "line10-15";
227 compatible = "gd,gd32-fwdgt";
233 compatible = "gd,gd32-wwdgt";
241 pinctrl: pin-controller@40010800 {
242 compatible = "gd,gd32-pinctrl-afio";
244 #address-cells = <1>;
245 #size-cells = <1>;
249 compatible = "gd,gd32-gpio";
251 gpio-controller;
252 #gpio-cells = <2>;
259 compatible = "gd,gd32-gpio";
261 gpio-controller;
262 #gpio-cells = <2>;
269 compatible = "gd,gd32-gpio";
271 gpio-controller;
272 #gpio-cells = <2>;
279 compatible = "gd,gd32-gpio";
281 gpio-controller;
282 #gpio-cells = <2>;
289 compatible = "gd,gd32-gpio";
291 gpio-controller;
292 #gpio-cells = <2>;
300 compatible = "gd,gd32-timer";
303 interrupt-names = "brk", "up", "trgcom", "cc";
306 is-advanced;
307 channels = <4>;
311 compatible = "gd,gd32-pwm";
313 #pwm-cells = <3>;
318 compatible = "gd,gd32-timer";
321 interrupt-names = "global";
324 channels = <4>;
328 compatible = "gd,gd32-pwm";
330 #pwm-cells = <3>;
335 compatible = "gd,gd32-timer";
338 interrupt-names = "global";
341 channels = <4>;
345 compatible = "gd,gd32-pwm";
347 #pwm-cells = <3>;
352 compatible = "gd,gd32-timer";
355 interrupt-names = "global";
358 channels = <4>;
362 compatible = "gd,gd32-pwm";
364 #pwm-cells = <3>;
369 compatible = "gd,gd32-timer";
372 interrupt-names = "global";
375 channels = <4>;
379 compatible = "gd,gd32-pwm";
381 #pwm-cells = <3>;
386 compatible = "gd,gd32-timer";
389 interrupt-names = "global";
392 channels = <0>;
397 compatible = "gd,gd32-timer";
400 interrupt-names = "global";
403 channels = <0>;
408 compatible = "gd,gd32-dma";
413 dma-channels = <7>;
415 #dma-cells = <2>;
420 compatible = "gd,gd32-dma";
425 dma-channels = <5>;
427 #dma-cells = <2>;