Lines Matching +full:num +full:- +full:channels
4 * SPDX-License-Identifier: Apache-2.0
63 uint32_t channels; member
81 struct dma_gd32_channel *channels; member
227 gd32_dma_transfer_number_config(uint32_t reg, dma_channel_enum ch, uint32_t num) in gd32_dma_transfer_number_config() argument
229 GD32_DMA_CHCNT(reg, ch) = (num & DMA_CHXCNT_CNT); in gd32_dma_transfer_number_config()
245 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_interrupt_flag_clear()
259 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_flag_clear()
273 return (DMA_INTF1(reg) & DMA_FLAG_ADD(flag, ch - DMA_CH4)); in gd32_dma_interrupt_flag_get()
294 DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, ch - DMA_CH4); in gd32_dma_deinit()
342 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_config()
343 struct dma_gd32_data *data = dev->data; in dma_gd32_config()
349 if (channel >= cfg->channels) { in dma_gd32_config()
351 cfg->channels, channel); in dma_gd32_config()
352 return -EINVAL; in dma_gd32_config()
355 if (dma_cfg->block_count != 1) { in dma_gd32_config()
357 return -ENOTSUP; in dma_gd32_config()
360 if (dma_cfg->channel_priority > 3) { in dma_gd32_config()
362 dma_cfg->channel_priority); in dma_gd32_config()
363 return -EINVAL; in dma_gd32_config()
366 if (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_DECREMENT) { in dma_gd32_config()
368 return -ENOTSUP; in dma_gd32_config()
371 if (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_DECREMENT) { in dma_gd32_config()
373 return -ENOTSUP; in dma_gd32_config()
376 if (dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_INCREMENT && in dma_gd32_config()
377 dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) { in dma_gd32_config()
379 dma_cfg->head_block->source_addr_adj); in dma_gd32_config()
380 return -ENOTSUP; in dma_gd32_config()
382 if (dma_cfg->head_block->dest_addr_adj != DMA_ADDR_ADJ_INCREMENT && in dma_gd32_config()
383 dma_cfg->head_block->dest_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) { in dma_gd32_config()
385 dma_cfg->head_block->dest_addr_adj); in dma_gd32_config()
386 return -ENOTSUP; in dma_gd32_config()
389 if (dma_cfg->source_data_size != 1 && dma_cfg->source_data_size != 2 && in dma_gd32_config()
390 dma_cfg->source_data_size != 4) { in dma_gd32_config()
392 dma_cfg->source_data_size); in dma_gd32_config()
393 return -EINVAL; in dma_gd32_config()
396 if (dma_cfg->dest_data_size != 1 && dma_cfg->dest_data_size != 2 && in dma_gd32_config()
397 dma_cfg->dest_data_size != 4) { in dma_gd32_config()
399 dma_cfg->dest_data_size); in dma_gd32_config()
400 return -EINVAL; in dma_gd32_config()
403 if (dma_cfg->channel_direction > PERIPHERAL_TO_MEMORY) { in dma_gd32_config()
407 dma_cfg->channel_direction); in dma_gd32_config()
408 return -ENOTSUP; in dma_gd32_config()
411 if (dma_cfg->channel_direction == MEMORY_TO_MEMORY && !cfg->mem2mem) { in dma_gd32_config()
413 return -ENOTSUP; in dma_gd32_config()
417 if (dma_cfg->dma_slot > 0xF) { in dma_gd32_config()
419 dma_cfg->dma_slot); in dma_gd32_config()
420 return -EINVAL; in dma_gd32_config()
424 gd32_dma_deinit(cfg->reg, channel); in dma_gd32_config()
426 src_cfg.addr = dma_cfg->head_block->source_address; in dma_gd32_config()
427 src_cfg.adj = dma_cfg->head_block->source_addr_adj; in dma_gd32_config()
428 src_cfg.width = dma_cfg->source_data_size; in dma_gd32_config()
430 dst_cfg.addr = dma_cfg->head_block->dest_address; in dma_gd32_config()
431 dst_cfg.adj = dma_cfg->head_block->dest_addr_adj; in dma_gd32_config()
432 dst_cfg.width = dma_cfg->dest_data_size; in dma_gd32_config()
434 switch (dma_cfg->channel_direction) { in dma_gd32_config()
436 gd32_dma_transfer_set_memory_to_memory(cfg->reg, channel); in dma_gd32_config()
441 gd32_dma_transfer_set_periph_to_memory(cfg->reg, channel); in dma_gd32_config()
446 gd32_dma_transfer_set_memory_to_periph(cfg->reg, channel); in dma_gd32_config()
452 gd32_dma_memory_address_config(cfg->reg, channel, memory_cfg->addr); in dma_gd32_config()
453 if (memory_cfg->adj == DMA_ADDR_ADJ_INCREMENT) { in dma_gd32_config()
454 gd32_dma_memory_increase_enable(cfg->reg, channel); in dma_gd32_config()
456 gd32_dma_memory_increase_disable(cfg->reg, channel); in dma_gd32_config()
459 gd32_dma_periph_address_config(cfg->reg, channel, periph_cfg->addr); in dma_gd32_config()
460 if (periph_cfg->adj == DMA_ADDR_ADJ_INCREMENT) { in dma_gd32_config()
461 gd32_dma_periph_increase_enable(cfg->reg, channel); in dma_gd32_config()
463 gd32_dma_periph_increase_disable(cfg->reg, channel); in dma_gd32_config()
466 gd32_dma_transfer_number_config(cfg->reg, channel, in dma_gd32_config()
467 dma_cfg->head_block->block_size); in dma_gd32_config()
468 gd32_dma_priority_config(cfg->reg, channel, in dma_gd32_config()
469 dma_gd32_priority(dma_cfg->channel_priority)); in dma_gd32_config()
470 gd32_dma_memory_width_config(cfg->reg, channel, in dma_gd32_config()
471 dma_gd32_memory_width(memory_cfg->width)); in dma_gd32_config()
472 gd32_dma_periph_width_config(cfg->reg, channel, in dma_gd32_config()
473 dma_gd32_periph_width(periph_cfg->width)); in dma_gd32_config()
474 gd32_dma_circulation_disable(cfg->reg, channel); in dma_gd32_config()
476 if (dma_cfg->channel_direction != MEMORY_TO_MEMORY) { in dma_gd32_config()
477 gd32_dma_channel_subperipheral_select(cfg->reg, channel, in dma_gd32_config()
478 dma_cfg->dma_slot); in dma_gd32_config()
482 data->channels[channel].callback = dma_cfg->dma_callback; in dma_gd32_config()
483 data->channels[channel].user_data = dma_cfg->user_data; in dma_gd32_config()
484 data->channels[channel].direction = dma_cfg->channel_direction; in dma_gd32_config()
492 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_reload()
493 struct dma_gd32_data *data = dev->data; in dma_gd32_reload()
495 if (ch >= cfg->channels) { in dma_gd32_reload()
497 cfg->channels, ch); in dma_gd32_reload()
498 return -EINVAL; in dma_gd32_reload()
501 if (data->channels[ch].busy) { in dma_gd32_reload()
502 return -EBUSY; in dma_gd32_reload()
505 gd32_dma_channel_disable(cfg->reg, ch); in dma_gd32_reload()
507 gd32_dma_transfer_number_config(cfg->reg, ch, size); in dma_gd32_reload()
509 switch (data->channels[ch].direction) { in dma_gd32_reload()
512 gd32_dma_memory_address_config(cfg->reg, ch, dst); in dma_gd32_reload()
513 gd32_dma_periph_address_config(cfg->reg, ch, src); in dma_gd32_reload()
516 gd32_dma_memory_address_config(cfg->reg, ch, src); in dma_gd32_reload()
517 gd32_dma_periph_address_config(cfg->reg, ch, dst); in dma_gd32_reload()
521 gd32_dma_channel_enable(cfg->reg, ch); in dma_gd32_reload()
528 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_start()
529 struct dma_gd32_data *data = dev->data; in dma_gd32_start()
531 if (ch >= cfg->channels) { in dma_gd32_start()
533 cfg->channels, ch); in dma_gd32_start()
534 return -EINVAL; in dma_gd32_start()
537 gd32_dma_interrupt_enable(cfg->reg, ch, in dma_gd32_start()
539 gd32_dma_channel_enable(cfg->reg, ch); in dma_gd32_start()
540 data->channels[ch].busy = true; in dma_gd32_start()
547 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_stop()
548 struct dma_gd32_data *data = dev->data; in dma_gd32_stop()
550 if (ch >= cfg->channels) { in dma_gd32_stop()
552 cfg->channels, ch); in dma_gd32_stop()
553 return -EINVAL; in dma_gd32_stop()
557 cfg->reg, ch, DMA_CHXCTL_FTFIE | GD32_DMA_INTERRUPT_ERRORS); in dma_gd32_stop()
558 gd32_dma_interrupt_flag_clear(cfg->reg, ch, in dma_gd32_stop()
560 gd32_dma_channel_disable(cfg->reg, ch); in dma_gd32_stop()
561 data->channels[ch].busy = false; in dma_gd32_stop()
569 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_get_status()
570 struct dma_gd32_data *data = dev->data; in dma_gd32_get_status()
572 if (ch >= cfg->channels) { in dma_gd32_get_status()
574 cfg->channels, ch); in dma_gd32_get_status()
575 return -EINVAL; in dma_gd32_get_status()
578 stat->pending_length = gd32_dma_transfer_number_get(cfg->reg, ch); in dma_gd32_get_status()
579 stat->dir = data->channels[ch].direction; in dma_gd32_get_status()
580 stat->busy = data->channels[ch].busy; in dma_gd32_get_status()
602 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_init()
605 (clock_control_subsys_t)&cfg->clkid); in dma_gd32_init()
608 (void)reset_line_toggle_dt(&cfg->reset); in dma_gd32_init()
611 for (uint32_t i = 0; i < cfg->channels; i++) { in dma_gd32_init()
612 gd32_dma_interrupt_disable(cfg->reg, i, in dma_gd32_init()
614 gd32_dma_deinit(cfg->reg, i); in dma_gd32_init()
617 cfg->irq_configure(); in dma_gd32_init()
624 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_isr()
625 struct dma_gd32_data *data = dev->data; in dma_gd32_isr()
629 for (uint32_t i = 0; i < cfg->channels; i++) { in dma_gd32_isr()
630 errflag = gd32_dma_interrupt_flag_get(cfg->reg, i, in dma_gd32_isr()
633 gd32_dma_interrupt_flag_get(cfg->reg, i, DMA_FLAG_FTF); in dma_gd32_isr()
640 err = -EIO; in dma_gd32_isr()
644 cfg->reg, i, DMA_FLAG_FTF | GD32_DMA_FLAG_ERRORS); in dma_gd32_isr()
645 data->channels[i].busy = false; in dma_gd32_isr()
647 if (data->channels[i].callback) { in dma_gd32_isr()
648 data->channels[i].callback( in dma_gd32_isr()
649 dev, data->channels[i].user_data, i, err); in dma_gd32_isr()
678 .channels = DT_INST_PROP(inst, dma_channels), \
696 .channels = dma_gd32##inst##_channels, \