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Searched refs:irq2 (Results 1 – 25 of 26) sorted by relevance

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/Zephyr-latest/tests/kernel/gen_isr_table/src/
Dmultilevel_irq.c11 static void test_multi_level_bit_masks_fn(uint32_t irq1, uint32_t irq2, uint32_t irq3) in test_multi_level_bit_masks_fn() argument
16 const uint32_t hwirq2 = irq2 - 1; in test_multi_level_bit_masks_fn()
18 const uint32_t irqn_l2 = (irq2 << l2_shift) | irqn_l1; in test_multi_level_bit_masks_fn()
24 } else if (IS_ENABLED(CONFIG_2ND_LEVEL_INTERRUPTS) && (irq2 > 0)) { in test_multi_level_bit_masks_fn()
31 if (irq2 > 0) { in test_multi_level_bit_masks_fn()
59 } else if (irq2 > 0) { in test_multi_level_bit_masks_fn()
92 uint32_t irq1, irq2; in ZTEST() local
97 irq2 = 1; in ZTEST()
98 test_multi_level_bit_masks_fn(irq1, irq2, 0); in ZTEST()
102 irq2 = BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
[all …]
/Zephyr-latest/tests/kernel/interrupt/src/
Ddynamic_shared_irq.c11 unsigned int irq2; member
40 arch_irq_disconnect_dynamic(fixture.irq2, fixture.irq_priority, in dynamic_shared_irq_suite_after()
89 fixture.irq2 = get_irq_slot(fixture.irq1 + 1); in dynamic_shared_irq_suite_setup()
90 zassert_true(fixture.irq2 != TEST_INVALID_IRQ, in dynamic_shared_irq_suite_setup()
95 fixture.irq2_table_idx = fixture.irq2 - CONFIG_GEN_IRQ_START_VECTOR; in dynamic_shared_irq_suite_setup()
138 arch_irq_connect_dynamic(fixture.irq2, fixture.irq_priority, in dynamic_shared_irq_suite_before()
165 irq_enable(fixture.irq2); in ZTEST()
168 trigger_irq(fixture.irq2); in ZTEST()
180 irq_disable(fixture.irq2); in ZTEST()
/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483.c295 uint8_t irq1, irq2; in nx20p3483_irq_worker() local
304 ret = read_reg(dev, NX20P3483_REG_INT2, &irq2); in nx20p3483_irq_worker()
331 if (irq1 & NX20P3483_REG_INT1_OV_5VSRC || irq2 & NX20P3483_REG_INT2_OV_HVSRC) { in nx20p3483_irq_worker()
336 if (irq1 & NX20P3483_REG_INT1_RCP_5VSRC || irq2 & NX20P3483_REG_INT2_RCP_HVSRC) { in nx20p3483_irq_worker()
341 if (irq1 & NX20P3483_REG_INT1_OC_5VSRC || irq2 & NX20P3483_REG_INT2_OC_HVSRC) { in nx20p3483_irq_worker()
346 if (irq1 & NX20P3483_REG_INT1_SC_5VSRC || irq2 & NX20P3483_REG_INT2_SC_HVSRC) { in nx20p3483_irq_worker()
352 if (irq2 & NX20P3483_REG_INT2_RCP_HVSNK) { in nx20p3483_irq_worker()
357 if (irq2 & NX20P3483_REG_INT2_SC_HVSNK) { in nx20p3483_irq_worker()
362 if (irq2 & NX20P3483_REG_INT2_OV_HVSNK) { in nx20p3483_irq_worker()
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi210 port-irq-names = "port-irq2",
216 port-irq2-pins = <10>;
228 "port-irq2",
232 port-irq2-pins = <13>;
261 "port-irq2",
264 port-irq2-pins = <1>;
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4m1ax.dtsi244 port-irq-names = "port-irq2",
250 port-irq2-pins = <2>;
263 "port-irq2",
268 port-irq2-pins = <0>;
278 "port-irq2",
282 port-irq2-pins = <13>;
Dr7fa4w1ad2cng.dtsi194 "port-irq2",
199 port-irq2-pins = <0>;
209 "port-irq2",
213 port-irq2-pins = <13>;
Dr7fa4e10x.dtsi215 "port-irq2",
220 port-irq2-pins = <0>;
230 "port-irq2",
234 port-irq2-pins = <13>;
Dr7fa4e2b93cfm.dtsi258 "port-irq2",
263 port-irq2-pins = <0>;
273 "port-irq2",
277 port-irq2-pins = <13>;
Dr7fa4m2ax.dtsi300 "port-irq2",
305 port-irq2-pins = <0>;
315 "port-irq2",
319 port-irq2-pins = <13>;
Dr7fa4m3ax.dtsi310 "port-irq2",
315 port-irq2-pins = <0>;
325 "port-irq2",
329 port-irq2-pins = <3 13>;
Dr7fa4l1bx.dtsi672 "port-irq2",
677 port-irq2-pins = <0>;
687 "port-irq2",
692 port-irq2-pins = <13>;
/Zephyr-latest/scripts/build/
Dgen_isr_tables.py199 irq2 = (irq & self.int_lvl_masks[1]) >> (self.int_bits[0])
203 list_index = self.get_irq_index(irq2 - 1, 3)
210 if irq2:
212 irq2_pos = self.get_irq_baseoffset(2) + self.__max_irq_per * list_index + irq2 - 1
214 self.__log.debug('IRQ_Indx = ' + str(irq2))
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi278 "port-irq2";
281 port-irq2-pins = <0>;
289 "port-irq2",
293 port-irq2-pins = <3 13>;
340 "port-irq2",
345 port-irq2-pins = <9>;
Dr7fa8m1xh.dtsi297 "port-irq2";
300 port-irq2-pins = <0>;
308 "port-irq2",
312 port-irq2-pins = <3 13>;
359 "port-irq2",
364 port-irq2-pins = <9>;
Dr7fa8d1xh.dtsi333 "port-irq2";
336 port-irq2-pins = <0>;
344 "port-irq2",
348 port-irq2-pins = <3 13>;
395 "port-irq2",
400 port-irq2-pins = <9>;
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi206 "port-irq2",
211 port-irq2-pins = <0>;
221 "port-irq2",
225 port-irq2-pins = <13>;
Dr7fa6e2bx.dtsi256 "port-irq2",
261 port-irq2-pins = <0>;
271 "port-irq2",
275 port-irq2-pins = <13>;
Dr7fa6m2ax.dtsi238 "port-irq2",
243 port-irq2-pins = <0>;
253 "port-irq2",
257 port-irq2-pins = <3 13>;
Dr7fa6e10x.dtsi279 "port-irq2",
284 port-irq2-pins = <0>;
294 "port-irq2",
298 port-irq2-pins = <13>;
Dr7fa6m5xh.dtsi482 "port-irq2",
487 port-irq2-pins = <0>;
497 "port-irq2",
501 port-irq2-pins = <3 13>;
579 "port-irq2",
583 port-irq2-pins = <3>;
Dr7fa6m3ax.dtsi304 "port-irq2",
309 port-irq2-pins = <0>;
319 "port-irq2",
323 port-irq2-pins = <3 13>;
Dr7fa6m4ax.dtsi405 "port-irq2",
410 port-irq2-pins = <0>;
420 "port-irq2",
424 port-irq2-pins = <3 13>;
/Zephyr-latest/drivers/mbox/
Dmbox_nrf_bellboard_rx.c172 BELLBOARD_IRQ_CONFIGURE(irq2, 2); in bellboard_rx_init()
/Zephyr-latest/dts/arm/renesas/rz/rzg/
Dr9a08g045.dtsi787 irq2: irq2 { label
/Zephyr-latest/dts/arm/renesas/rz/rzn/
Dr9a07g084.dtsi115 irq2: irq@2 { label

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