Home
last modified time | relevance | path

Searched refs:irq1 (Results 1 – 25 of 26) sorted by relevance

12

/Zephyr-latest/tests/kernel/gen_isr_table/src/
Dmultilevel_irq.c11 static void test_multi_level_bit_masks_fn(uint32_t irq1, uint32_t irq2, uint32_t irq3) in test_multi_level_bit_masks_fn() argument
15 const uint32_t hwirq1 = irq1; in test_multi_level_bit_masks_fn()
17 const uint32_t irqn_l1 = irq1; in test_multi_level_bit_masks_fn()
71 uint32_t irq1; in ZTEST() local
74 irq1 = 0; in ZTEST()
75 test_multi_level_bit_masks_fn(irq1, 0, 0); in ZTEST()
78 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
79 test_multi_level_bit_masks_fn(irq1, 0, 0); in ZTEST()
82 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS); in ZTEST()
83 test_multi_level_bit_masks_fn(irq1, 0, 0); in ZTEST()
[all …]
/Zephyr-latest/tests/kernel/interrupt/src/
Ddynamic_shared_irq.c10 unsigned int irq1; member
36 arch_irq_disconnect_dynamic(fixture.irq1, fixture.irq_priority, in dynamic_shared_irq_suite_after()
38 arch_irq_disconnect_dynamic(fixture.irq1, fixture.irq_priority, in dynamic_shared_irq_suite_after()
86 fixture.irq1 = get_irq_slot(CONFIG_GEN_IRQ_START_VECTOR); in dynamic_shared_irq_suite_setup()
87 zassert_true(fixture.irq1 != TEST_INVALID_IRQ, in dynamic_shared_irq_suite_setup()
89 fixture.irq2 = get_irq_slot(fixture.irq1 + 1); in dynamic_shared_irq_suite_setup()
94 fixture.irq1_table_idx = fixture.irq1 - CONFIG_GEN_IRQ_START_VECTOR; in dynamic_shared_irq_suite_setup()
110 arch_irq_connect_dynamic(fixture.irq1, fixture.irq_priority, in dynamic_shared_irq_suite_before()
120 arch_irq_connect_dynamic(fixture.irq1, fixture.irq_priority, in dynamic_shared_irq_suite_before()
164 irq_enable(fixture.irq1); in ZTEST()
[all …]
/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483.c295 uint8_t irq1, irq2; in nx20p3483_irq_worker() local
298 ret = read_reg(dev, NX20P3483_REG_INT1, &irq1); in nx20p3483_irq_worker()
311 LOG_DBG("No callback set: %02x %02x", irq1, irq1); in nx20p3483_irq_worker()
315 if (irq1 & NX20P3483_REG_INT1_DBEXIT_ERR) { in nx20p3483_irq_worker()
320 if (irq1 & NX20P3483_REG_INT1_OTP) { in nx20p3483_irq_worker()
325 if (irq1 & NX20P3483_REG_INT2_EN_ERR) { in nx20p3483_irq_worker()
331 if (irq1 & NX20P3483_REG_INT1_OV_5VSRC || irq2 & NX20P3483_REG_INT2_OV_HVSRC) { in nx20p3483_irq_worker()
336 if (irq1 & NX20P3483_REG_INT1_RCP_5VSRC || irq2 & NX20P3483_REG_INT2_RCP_HVSRC) { in nx20p3483_irq_worker()
341 if (irq1 & NX20P3483_REG_INT1_OC_5VSRC || irq2 & NX20P3483_REG_INT2_OC_HVSRC) { in nx20p3483_irq_worker()
346 if (irq1 & NX20P3483_REG_INT1_SC_5VSRC || irq2 & NX20P3483_REG_INT2_SC_HVSRC) { in nx20p3483_irq_worker()
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4w1ad2cng.dtsi193 "port-irq1",
198 port-irq1-pins = <1 4>;
208 "port-irq1",
212 port-irq1-pins = <5>;
Dr7fa4e10x.dtsi214 "port-irq1",
219 port-irq1-pins = <1 4>;
229 "port-irq1",
233 port-irq1-pins = <5>;
Dr7fa4e2b93cfm.dtsi257 "port-irq1",
262 port-irq1-pins = <1 4>;
272 "port-irq1",
276 port-irq1-pins = <5>;
Dr7fa4m1ax.dtsi262 "port-irq1",
267 port-irq1-pins = <1 4>;
277 "port-irq1",
281 port-irq1-pins = <5>;
Dr7fa4m2ax.dtsi299 "port-irq1",
304 port-irq1-pins = <1 4>;
314 "port-irq1",
318 port-irq1-pins = <5>;
Dr7fa4m3ax.dtsi309 "port-irq1",
314 port-irq1-pins = <1 4>;
324 "port-irq1",
328 port-irq1-pins = <5>;
Dr7fa4l1bx.dtsi671 "port-irq1",
676 port-irq1-pins = <1 4>;
686 "port-irq1",
691 port-irq1-pins = <5>;
/Zephyr-latest/scripts/build/
Dgen_isr_tables.py200 irq1 = irq & self.int_lvl_masks[0]
211 list_index = self.get_irq_index(irq1, 2)
219 self.__log.debug('IRQ_Indx = ' + str(irq1))
220 self.__log.debug('IRQ_Pos = ' + str(irq1))
221 return irq1 - offset
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi277 "port-irq1",
280 port-irq1-pins = <1 4>;
288 "port-irq1",
292 port-irq1-pins = <5>;
339 port-irq-names = "port-irq1",
344 port-irq1-pins = <8>;
Dr7fa8m1xh.dtsi296 "port-irq1",
299 port-irq1-pins = <1 4>;
307 "port-irq1",
311 port-irq1-pins = <5>;
358 port-irq-names = "port-irq1",
363 port-irq1-pins = <8>;
Dr7fa8d1xh.dtsi332 "port-irq1",
335 port-irq1-pins = <1 4>;
343 "port-irq1",
347 port-irq1-pins = <5>;
394 port-irq-names = "port-irq1",
399 port-irq1-pins = <8>;
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi249 "port-irq1",
253 port-irq1-pins = <7 8>;
260 port-irq-names = "port-irq1",
263 port-irq1-pins = <2>;
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi205 "port-irq1",
210 port-irq1-pins = <1 4>;
220 "port-irq1",
224 port-irq1-pins = <5>;
Dr7fa6e2bx.dtsi255 "port-irq1",
260 port-irq1-pins = <1 4>;
270 "port-irq1",
274 port-irq1-pins = <5>;
Dr7fa6m2ax.dtsi237 "port-irq1",
242 port-irq1-pins = <1 4>;
252 "port-irq1",
256 port-irq1-pins = <5>;
Dr7fa6e10x.dtsi278 "port-irq1",
283 port-irq1-pins = <1 4>;
293 "port-irq1",
297 port-irq1-pins = <5>;
Dr7fa6m5xh.dtsi481 "port-irq1",
486 port-irq1-pins = <1 4>;
496 "port-irq1",
500 port-irq1-pins = <5>;
578 "port-irq1",
582 port-irq1-pins = <4>;
Dr7fa6m3ax.dtsi303 "port-irq1",
308 port-irq1-pins = <1 4>;
318 "port-irq1",
322 port-irq1-pins = <5>;
Dr7fa6m4ax.dtsi404 "port-irq1",
409 port-irq1-pins = <1 4>;
419 "port-irq1",
423 port-irq1-pins = <5>;
/Zephyr-latest/drivers/mbox/
Dmbox_nrf_bellboard_rx.c171 BELLBOARD_IRQ_CONFIGURE(irq1, 1); in bellboard_rx_init()
/Zephyr-latest/dts/arm/renesas/rz/rzg/
Dr9a08g045.dtsi780 irq1: irq1 { label
/Zephyr-latest/dts/arm/renesas/rz/rzn/
Dr9a07g084.dtsi106 irq1: irq@1 { label

12