Home
last modified time | relevance | path

Searched +full:revision +full:- +full:reg (Results 1 – 25 of 48) sorted by relevance

12

/Zephyr-latest/dts/bindings/misc/
Dnuvoton,npcx-soc-id.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nuvoton,npcx-soc-id"
9 family-id:
14 chip-id:
19 device-id:
24 revision-reg:
27 description: NPCX revision register address & length in byte
/Zephyr-latest/include/zephyr/usb_c/
Dtcpci.h3 * SPDX-License-Identifier: Apache-2.0
15 * Registers and fields are compliant to the Type-C Port Controller Interface
16 * Specification Revision 2.0, Version 1.3.
19 /** Register address - vendor id */
22 /** Register address - product id */
25 /** Register address - version of TCPC */
28 /** Register address - USB TypeC version */
30 /** Mask for major part of type-c release supported */
32 /** Macro to extract the major part of type-c release supported */
33 #define TCPC_REG_TC_REV_MAJOR(reg) (((reg) & TCPC_REG_TC_REV_MAJOR_MASK) >> 4) argument
[all …]
/Zephyr-latest/dts/bindings/dma/
Dnxp,mcux-edma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
11 reg:
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
33 channel-gap:
47 irq-shared-offset:
54 no-error-irq:
[all …]
/Zephyr-latest/doc/hardware/porting/
Dshields.rst6 Shields, also known as "add-on" or "daughter boards", attach to a board
8 In Zephyr, the shield feature provides Zephyr-formatted shield
17 .. code-block:: none
27 format that is merged with the board's :ref:`devicetree <dt-guide>`
44 .. code-block:: devicetree
47 reg = <1>;
72 Hardware shield-to-board compatibility depends on the use of well-known
81 * Devicetree: A board :ref:`devicetree <dt-guide>` file,
85 .. code-block:: devicetree
90 -----------------------------------
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
14 * eight regions. Zephyr has an in-tree CMSIS header located in the arch
16 * from hal_cmsis based on the k-config CPU selection.
17 * The Zephyr in-tree header does not provide all the symbols ARM CMSIS
19 * MPU present to 0. We define these two symbols here based on our k-config
20 * selections. NOTE: Zephyr in-tree CMSIS defines the Cortex-M4 hardware
21 * revision to 0. At this time ARM CMSIS does not appear to use the hardware
22 * revision in any macros.
27 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
33 #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
[all …]
/Zephyr-latest/boards/st/stm32wb5mmg/doc/
Dstm32wb5mmg.rst6 STM32WB5MMG is an ultra-low-power and small form factor certified 2.4 GHz
7 wireless module. It supports Bluetooth|reg| Low Energy 5.4, Zigbee|reg| 3.0,
10 module on other boards as HCI layer (Specefically B-U585I-IOT02A Development board).
14 - Bluetooth module in SiP-LGA86 package
15 - Integrated chip antenna
16 - Bluetooth|reg| Low Energy 5.4, Zigbee|reg| 3.0, OpenThread certified
18 - IEEE 802.15.4-2011 MAC PHY Supports 2 Mbits/s
19 - Frequency band 2402-2480 MHz
20 - Advertising extension
21 - Tx output power up to +6 dBm
[all …]
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f0/stm32f070cbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/led/led.h>
11 #include <zephyr/dt-bindings/led/seagate_legend_b1414.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 zephyr,shell-uart = &usart1;
24 led-strip = &led_strip_spi;
27 board_id: brd-id {
28 compatible = "gpio-keys";
[all …]
/Zephyr-latest/drivers/adc/
Dadc_sam0.c4 * SPDX-License-Identifier: Apache-2.0
73 const struct adc_sam0_cfg *const cfg = dev->config; in adc_sam0_acquisition_to_clocks()
79 return -EINVAL; in adc_sam0_acquisition_to_clocks()
82 return (int)ADC_ACQ_TIME_VALUE(acquisition_time) - 1; in adc_sam0_acquisition_to_clocks()
92 return -EINVAL; in adc_sam0_acquisition_to_clocks()
97 * sample_length = sample_time * (2/clk_adc) - 1, in adc_sam0_acquisition_to_clocks()
101 scaled_acq += cfg->freq / 2U; in adc_sam0_acquisition_to_clocks()
102 scaled_acq /= cfg->freq; in adc_sam0_acquisition_to_clocks()
107 scaled_acq -= 1U; in adc_sam0_acquisition_to_clocks()
109 return -EINVAL; in adc_sam0_acquisition_to_clocks()
[all …]
/Zephyr-latest/drivers/usb/uhc/
Duhc_max3421e.h4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX3421E_CMD_SPI_READ(reg) \ argument
21 (((reg) << MAX3421E_CMD_REG_SHIFT) | MAX3421E_CMD_DIR_RD)
23 #define MAX3421E_CMD_SPI_WRITE(reg) \ argument
24 (((reg) << MAX3421E_CMD_REG_SHIFT) | MAX3421E_CMD_DIR_WR)
77 /* Register REVISION */
184 /* Bad value in HXFR reg */
192 /* Toggle error/ISO over-underrun */
204 /* K-state instead of response */
206 /* J-state instead of response */
/Zephyr-latest/drivers/can/
Dcan_tcan4x5x.c4 * SPDX-License-Identifier: Apache-2.0
21 * The register definitions correspond to those found in the TI TCAN4550-Q1 datasheet, revision D
31 /* Revision register */
241 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_read()
242 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_read()
271 /* Maximum transfer size is 256 32-bit words */ in tcan4x5x_read()
275 err = spi_transceive_dt(&tcan_config->spi, &tx, &rx); in tcan4x5x_read()
292 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_write()
293 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_write()
321 /* Maximum transfer size is 256 32-bit words */ in tcan4x5x_write()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_stmpe1600.c4 * SPDX-License-Identifier: Apache-2.0
10 * @file Driver for STMPE1600 I2C-based GPIO driver.
31 #define REG_VERSION_ID 0x02 /* Revision number (const 0x01) */
69 static int write_reg16(const struct stmpe1600_config * const config, uint8_t reg, uint16_t value) in write_reg16() argument
74 LOG_DBG("STMPE1600[0x%02X]: write REG[0x%02X..0x%02X] = %04x", in write_reg16()
75 config->i2c.addr, reg, reg + 1, value); in write_reg16()
77 buf[0] = reg; in write_reg16()
80 ret = i2c_write_dt(&config->i2c, buf, sizeof(buf)); in write_reg16()
83 LOG_ERR("STMPE1600[0x%02X]: write error REG[0x%02X..0x%02X]: %d", in write_reg16()
84 config->i2c.addr, reg, reg + 1, ret); in write_reg16()
[all …]
Dgpio_andes_atcgpio100.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
26 #define REG_IDR 0x00 /* ID and Revision reg. */
27 #define REG_CFG 0x10 /* Hardware configure reg. */
28 #define REG_DIN 0x20 /* Data In reg. */
29 #define REG_DOUT 0x24 /* Data Out reg. */
30 #define REG_DIR 0x28 /* Channel direction reg. */
31 #define REG_DCLR 0x2C /* Data out clear reg. */
32 #define REG_DSET 0x30 /* Data out set reg. */
33 #define REG_PUEN 0x40 /* Pull enable reg. */
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx7.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx7/npcx7-alts-map.dtsi"
10 #include "npcx7/npcx7-miwus-wui-map.dtsi"
12 #include "npcx7/npcx7-miwus-int-map.dtsi"
14 #include "npcx7/npcx7-espi-vws-map.dtsi"
15 /* NPCX7 series low-voltage io controls mapping table */
16 #include "npcx7/npcx7-lvol-ctrl-map.dtsi"
24 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
27 power-states {
28 suspend_to_idle0: suspend-to-idle0 {
[all …]
Dnpcx9.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx9/npcx9-alts-map.dtsi"
10 #include "npcx9/npcx9-miwus-wui-map.dtsi"
12 #include "npcx9/npcx9-miwus-int-map.dtsi"
14 #include "npcx9/npcx9-espi-vws-map.dtsi"
15 /* NPCX9 series low-voltage io controls mapping table */
16 #include "npcx9/npcx9-lvol-ctrl-map.dtsi"
24 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
27 power-states {
28 suspend_to_idle0: suspend-to-idle0 {
[all …]
Dnpcx4.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx4/npcx4-alts-map.dtsi"
10 #include "npcx4/npcx4-miwus-wui-map.dtsi"
12 #include "npcx4/npcx4-miwus-int-map.dtsi"
14 #include "npcx4/npcx4-espi-vws-map.dtsi"
15 /* npcx4 series low-voltage io controls mapping table */
16 #include "npcx4/npcx4-lvol-ctrl-map.dtsi"
18 #include "zephyr/dt-bindings/reset/npcx4_reset.h"
26 cpu-power-states = <&suspend_to_idle0>;
29 power-states {
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_andes_atcpit100.c4 * SPDX-License-Identifier: Apache-2.0
16 #define REG_IDR 0x00 /* ID and Revision Reg. */
17 #define REG_CFG 0x10 /* Configuration Reg. */
18 #define REG_INTE 0x14 /* Interrupt Enable Reg. */
19 #define REG_ISTA 0x18 /* Interrupt Status Reg. */
20 #define REG_CHEN 0x1C /* Channel Enable Reg. */
21 #define REG_CTRL0 0x20 /* Channel 0 Control Reg. */
22 #define REG_RELD0 0x24 /* Channel 0 Reload Reg. */
23 #define REG_CNTR0 0x28 /* Channel 0 Counter Reg. */
24 #define REG_CTRL1 0x30 /* Channel 1 Control Reg. */
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_smsc911x_priv.h1 /* SPDX-License-Identifier: Apache-2.0 */
4 * Copyright (c) 2018-2019 Linaro Limited
10 * http://www.apache.org/licenses/LICENSE-2.0
25 /* This file is the re-implementation of mps2_ethernet_api and Selftest's
27 * MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
28 * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
44 (((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
46 #define SMSC9220_BFIELD(reg, bfield) BFIELD(SMSC9220->reg, reg ## _ ## bfield) argument
69 /* Chip ID and Revision (offset 0x50) */
79 /* Read-only byte order testing register 87654321h (offset 0x64) */
[all …]
/Zephyr-latest/cmake/modules/
Dextensions.cmake1 # SPDX-License-Identifier: Apache-2.0
14 # 1. Zephyr-aware extensions
21 # 2. Kconfig-aware extensions
23 # 3. CMake-generic extensions
44 # 1. Zephyr-aware extensions
49 # "zephyr". zephyr is a catch-all CMake library for source files that
52 # [0] https://cmake.org/cmake/help/latest/manual/cmake-buildsystem.7.html
66 # As a very high-level introduction here are two call graphs that are
72 # zephyr_library_compile_options() --> target_compile_options()
75 # zephyr_cc_option() ---> target_cc_option()
[all …]
/Zephyr-latest/boards/st/stm32f412g_disco/doc/
Dindex.rst6 The STM32F412 Discovery kit features an ARM Cortex-M4 based STM32F412ZG MCU
8 some highlights of the STM32F412G-DISCO board:
11 - STM32F412ZGT6 microcontroller featuring 1 Mbyte of Flash memory and 256 Kbytes of RAM in an LQFP1…
12 - On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability:
14 - USB virtual COM port
15 - mass storage
16 - debug port
18 - 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen
19 - I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker …
20 - Stereo digital MEMS microphones
[all …]
/Zephyr-latest/boards/st/stm32f413h_disco/doc/
Dindex.rst6 The STM32F413H-DISCO Discovery kit features an ARM Cortex-M4 based STM32F413ZH MCU
8 some highlights of the STM32F413H-DISCO board:
11 - STM32F413ZHT6 microcontroller featuring 1.5 Mbyte of Flash memory and 320 Kbytes of RAM in an LQF…
12 - On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability:
14 - USB virtual COM port
15 - mass storage
16 - debug port
18 - 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen
19 - I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker …
20 - Stereo digital MEMS microphones
[all …]
/Zephyr-latest/boards/st/stm32f411e_disco/doc/
Dindex.rst6 The STM32F411E Discovery kit features an ARM Cortex-M4 based STM32F411VE MCU
8 Here are some highlights of the STM32F411E-DISCO board:
10 - STM32F411VET6 microcontroller featuring 512 KB of Flash memory, 128 KB of RAM in an LQFP100 packa…
11 - On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone STLINK/V2 (with SWD…
12 - Board power supply: through USB bus or from an external 5 V supply voltage
13 - External application power supply: 3 V and 5 V
14 - L3GD20(rev B) or I3G4250D(rev D): ST MEMS motion sensor, 3-axis digital output gyroscope.
15 - LSM303DLHC(rev B) or LSM303AGR(rev D): ST MEMS system-in-package featuring a 3D digital linear ac…
16 - MP45DT02(rev B) or IMP34DT05(rev D), ST MEMS audio sensor, omnidirectional digital microphone
17 - CS43L22, audio DAC with integrated class D speaker driver
[all …]
/Zephyr-latest/drivers/disk/nvme/
Dnvme_helpers.h2 * SPDX-License-Identifier: Apache-2.0
177 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
184 /* SR-IOV Virtual Function */
191 /** OAES - Optional Asynchronous Events Supported */
220 /** OACS - optional admin command support */
233 /* supports Device Self-test command */
239 /* supports NVMe-MI Send/Receive */
253 /* first slot is read-only */
268 /** AVSCC - admin vendor specific command configuration */
288 /* No-Deallocate Inhibited */
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7.dtsi7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
[all …]
/Zephyr-latest/boards/st/nucleo_l412rb_p/doc/
Dindex.rst6 The Nucleo L412RB board features an ARM Cortex-M4 based STM32L412RB MCU
10 - STM32 microcontroller in LQFP64 package
11 - 1 user LED shared with ARDUINO |reg|
12 - 1 user and 1 reset push-buttons
13 - 32.768 kHz crystal oscillator
14 - Two types of extension resources:
16 - Arduino Uno V3 connectivity
17 - ST morpho extension pin headers for full access to all STM32 I/Os
19 - On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual CO…
20 - Flexible power-supply options: ST-LINK, USB VBUS, or external sources
[all …]
/Zephyr-latest/drivers/serial/
Duart_sam0.c4 * SPDX-License-Identifier: Apache-2.0
26 * SERCOM revision 0x500
96 while ((usart->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_MASK) != 0) { in wait_synchronization()
100 while ((usart->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
118 return -ERANGE; in uart_sam0_set_baudrate()
121 baud = 65536 - (uint16_t)tmp; in uart_sam0_set_baudrate()
122 usart->BAUD.reg = baud; in uart_sam0_set_baudrate()
140 const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg; in uart_sam0_dma_tx_done()
142 SercomUsart * const regs = cfg->regs; in uart_sam0_dma_tx_done()
144 regs->INTENSET.reg = SERCOM_USART_INTENSET_TXC; in uart_sam0_dma_tx_done()
[all …]

12