Lines Matching +full:revision +full:- +full:reg
4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx9/npcx9-alts-map.dtsi"
10 #include "npcx9/npcx9-miwus-wui-map.dtsi"
12 #include "npcx9/npcx9-miwus-int-map.dtsi"
14 #include "npcx9/npcx9-espi-vws-map.dtsi"
15 /* NPCX9 series low-voltage io controls mapping table */
16 #include "npcx9/npcx9-lvol-ctrl-map.dtsi"
24 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
27 power-states {
28 suspend_to_idle0: suspend-to-idle0 {
29 compatible = "zephyr,power-state";
30 power-state-name = "suspend-to-idle";
31 substate-id = <0>;
32 min-residency-us = <1000>;
35 suspend_to_idle1: suspend-to-idle1 {
36 compatible = "zephyr,power-state";
37 power-state-name = "suspend-to-idle";
38 substate-id = <1>;
39 min-residency-us = <201000>;
44 def-io-conf-list {
83 compatible = "nuvoton,npcx9", "nuvoton,npcx", "simple-bus";
85 bbram: bb-ram@400af000 {
86 compatible = "nuvoton,npcx-bbram";
87 reg = <0x400af000 0x80
89 reg-names = "memory", "status";
94 compatible = "nuvoton,npcx-itim-timer";
95 reg = <0x400b0000 0x2000
97 reg-names = "evt_itim", "sys_itim";
104 compatible = "nuvoton,npcx-uart";
106 reg = <0x400E0000 0x2000 0x40011100 0x100>;
111 uart-rx = <&wui_cr_sin1>;
116 compatible = "nuvoton,npcx-uart";
118 reg = <0x400E2000 0x2000 0x40011200 0x100>;
123 uart-rx = <&wui_cr_sin2>;
128 compatible = "nuvoton,npcx-uart";
130 reg = <0x400E4000 0x2000 0x40011300 0x100>;
135 uart-rx = <&wui_cr_sin3>;
140 compatible = "nuvoton,npcx-uart";
142 reg = <0x400E6000 0x2000 0x40011400 0x100>;
147 uart-rx = <&wui_cr_sin4>;
152 pcc: clock-controller@4000d000 {
153 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
154 core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
155 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
156 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
157 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
158 apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
159 ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
160 pwdwn-ctl-val = <0xfb /* No FIU_PD */
170 /* Wake-up input source mapping for GPIOs in npcx9 series */
172 wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
175 lvol-maps = <&lvol_io00 &lvol_none &lvol_none &lvol_none
180 wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
183 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
188 wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
191 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
196 wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
199 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
204 wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
207 lvol-maps = <&lvol_io40 &lvol_none &lvol_none &lvol_none
212 wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
215 lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
220 wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
223 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
228 wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
231 lvol-maps = <&lvol_none &lvol_none &lvol_io72 &lvol_io73
236 wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
239 lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_none
244 wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
247 lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
252 wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
255 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
260 wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
263 lvol-maps = <&lvol_none &lvol_none &lvol_iob2 &lvol_iob3
268 wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
271 lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none
276 wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
279 lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_none &lvol_none
284 wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
287 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_ioe3
292 wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
295 lvol-maps = <&lvol_none &lvol_none &lvol_iof2 &lvol_iof3
301 channel-count = <12>;
302 threshold-count = <6>;
311 compatible = "nuvoton,npcx-sha";
312 reg = <0x13c 0x3c>;
313 context-buffer-size = <212>;
318 compatible = "nuvoton,npcx-shi";
319 reg = <0x4000f000 0x120>;
323 buffer-rx-size = <128>;
324 buffer-tx-size = <128>;
325 shi-cs-wui =<&wui_io53>;
329 rx-plsize = <64>;
330 tx-plsize = <16>;
333 rctl: reset-controller@400c3100 {
334 compatible = "nuvoton,npcx-rst";
335 reg = <0x400c3100 0x14>;
336 #reset-cells = <1>;
341 soc-id {
342 chip-id = <0x09>;
343 revision-reg = <0x0000FFFC 4>;