1 /* 2 * Copyright (c) 2019 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __MEC_SOC_H 8 #define __MEC_SOC_H 9 10 #ifndef _ASMLANGUAGE 11 12 /* 13 * MEC172x includes the ARM single precision FPU and the ARM MPU with 14 * eight regions. Zephyr has an in-tree CMSIS header located in the arch 15 * include hierarchy that includes the correct ARM CMSIS core_xxx header 16 * from hal_cmsis based on the k-config CPU selection. 17 * The Zephyr in-tree header does not provide all the symbols ARM CMSIS 18 * requires. Zephyr does not define CMSIS FPU present and defaults CMSIS 19 * MPU present to 0. We define these two symbols here based on our k-config 20 * selections. NOTE: Zephyr in-tree CMSIS defines the Cortex-M4 hardware 21 * revision to 0. At this time ARM CMSIS does not appear to use the hardware 22 * revision in any macros. 23 */ 24 #define __FPU_PRESENT CONFIG_CPU_HAS_FPU 25 #define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU 26 27 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */ 28 29 #define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */ 30 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 31 #define __Vendor_SysTickConfig 0 /*!< 0 use default SysTick HW */ 32 #define __FPU_DP 0 /*!< Set to 1 if FPU is double precision */ 33 #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ 34 #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ 35 #define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */ 36 37 /** @brief ARM Cortex-M4 NVIC Interrupt Numbers 38 * CM4 NVIC implements 16 internal interrupt sources. CMSIS macros use 39 * negative numbers [-15, -1]. Lower numerical value indicates higher 40 * priority. 41 * -15 = Reset Vector invoked on POR or any CPU reset. 42 * -14 = NMI 43 * -13 = Hard Fault. At POR or CPU reset all faults map to Hard Fault. 44 * -12 = Memory Management Fault. If enabled Hard Faults caused by access 45 * violations, no address match, or MPU mismatch. 46 * -11 = Bus Fault. If enabled pre-fetch, AHB access faults. 47 * -10 = Usage Fault. If enabled Undefined instructions, illegal state 48 * transition (Thumb -> ARM mode), unaligned, etc. 49 * -9 through -6 are not implemented (reserved). 50 * -5 System call via SVC instruction. 51 * -4 Debug Monitor. 52 * -3 not implemented (reserved). 53 * -2 PendSV for system service. 54 * -1 SysTick NVIC system timer. 55 * Numbers >= 0 are external peripheral interrupts. 56 */ 57 typedef enum { 58 /* ========== ARM Cortex-M4 Specific Interrupt Numbers ============ */ 59 60 Reset_IRQn = -15, /*!< POR/CPU Reset Vector */ 61 NonMaskableInt_IRQn = -14, /*!< NMI */ 62 HardFault_IRQn = -13, /*!< Hard Faults */ 63 MemoryManagement_IRQn = -12, /*!< Memory Management faults */ 64 BusFault_IRQn = -11, /*!< Bus Access faults */ 65 UsageFault_IRQn = -10, /*!< Usage/instruction faults */ 66 SVCall_IRQn = -5, /*!< SVC */ 67 DebugMonitor_IRQn = -4, /*!< Debug Monitor */ 68 PendSV_IRQn = -2, /*!< PendSV */ 69 SysTick_IRQn = -1, /*!< SysTick */ 70 71 /* ============== MEC172x Specific Interrupt Numbers ============ */ 72 73 GIRQ08_IRQn = 0, /*!< GPIO 0140 - 0176 */ 74 GIRQ09_IRQn = 1, /*!< GPIO 0100 - 0136 */ 75 GIRQ10_IRQn = 2, /*!< GPIO 0040 - 0076 */ 76 GIRQ11_IRQn = 3, /*!< GPIO 0000 - 0036 */ 77 GIRQ12_IRQn = 4, /*!< GPIO 0200 - 0236 */ 78 GIRQ13_IRQn = 5, /*!< SMBus Aggregated */ 79 GIRQ14_IRQn = 6, /*!< DMA Aggregated */ 80 GIRQ15_IRQn = 7, 81 GIRQ16_IRQn = 8, 82 GIRQ17_IRQn = 9, 83 GIRQ18_IRQn = 10, 84 GIRQ19_IRQn = 11, 85 GIRQ20_IRQn = 12, 86 GIRQ21_IRQn = 13, 87 /* GIRQ22(peripheral clock wake) is not connected to NVIC */ 88 GIRQ23_IRQn = 14, 89 GIRQ24_IRQn = 15, 90 GIRQ25_IRQn = 16, 91 GIRQ26_IRQn = 17, /*!< GPIO 0240 - 0276 */ 92 /* Reserved 18-19 */ 93 /* GIRQ's 8 - 12, 24 - 26 no direct connections */ 94 I2C_SMB_0_IRQn = 20, /*!< GIRQ13 b[0] */ 95 I2C_SMB_1_IRQn = 21, /*!< GIRQ13 b[1] */ 96 I2C_SMB_2_IRQn = 22, /*!< GIRQ13 b[2] */ 97 I2C_SMB_3_IRQn = 23, /*!< GIRQ13 b[3] */ 98 DMA0_IRQn = 24, /*!< GIRQ14 b[0] */ 99 DMA1_IRQn = 25, /*!< GIRQ14 b[1] */ 100 DMA2_IRQn = 26, /*!< GIRQ14 b[2] */ 101 DMA3_IRQn = 27, /*!< GIRQ14 b[3] */ 102 DMA4_IRQn = 28, /*!< GIRQ14 b[4] */ 103 DMA5_IRQn = 29, /*!< GIRQ14 b[5] */ 104 DMA6_IRQn = 30, /*!< GIRQ14 b[6] */ 105 DMA7_IRQn = 31, /*!< GIRQ14 b[7] */ 106 DMA8_IRQn = 32, /*!< GIRQ14 b[8] */ 107 DMA9_IRQn = 33, /*!< GIRQ14 b[9] */ 108 DMA10_IRQn = 34, /*!< GIRQ14 b[10] */ 109 DMA11_IRQn = 35, /*!< GIRQ14 b[11] */ 110 DMA12_IRQn = 36, /*!< GIRQ14 b[12] */ 111 DMA13_IRQn = 37, /*!< GIRQ14 b[13] */ 112 DMA14_IRQn = 38, /*!< GIRQ14 b[14] */ 113 DMA15_IRQn = 39, /*!< GIRQ14 b[15] */ 114 UART0_IRQn = 40, /*!< GIRQ15 b[0] */ 115 UART1_IRQn = 41, /*!< GIRQ15 b[1] */ 116 EMI0_IRQn = 42, /*!< GIRQ15 b[2] */ 117 EMI1_IRQn = 43, /*!< GIRQ15 b[3] */ 118 EMI2_IRQn = 44, /*!< GIRQ15 b[4] */ 119 ACPI_EC0_IBF_IRQn = 45, /*!< GIRQ15 b[5] */ 120 ACPI_EC0_OBE_IRQn = 46, /*!< GIRQ15 b[6] */ 121 ACPI_EC1_IBF_IRQn = 47, /*!< GIRQ15 b[7] */ 122 ACPI_EC1_OBE_IRQn = 48, /*!< GIRQ15 b[8] */ 123 ACPI_EC2_IBF_IRQn = 49, /*!< GIRQ15 b[9] */ 124 ACPI_EC2_OBE_IRQn = 50, /*!< GIRQ15 b[10] */ 125 ACPI_EC3_IBF_IRQn = 51, /*!< GIRQ15 b[11] */ 126 ACPI_EC3_OBE_IRQn = 52, /*!< GIRQ15 b[12] */ 127 ACPI_EC4_IBF_IRQn = 53, /*!< GIRQ15 b[13] */ 128 ACPI_EC4_OBE_IRQn = 54, /*!< GIRQ15 b[14] */ 129 ACPI_PM1_CTL_IRQn = 55, /*!< GIRQ15 b[15] */ 130 ACPI_PM1_EN_IRQn = 56, /*!< GIRQ15 b[16] */ 131 ACPI_PM1_STS_IRQn = 57, /*!< GIRQ15 b[17] */ 132 KBC_OBE_IRQn = 58, /*!< GIRQ15 b[18] */ 133 KBC_IBF_IRQn = 59, /*!< GIRQ15 b[19] */ 134 MBOX_IRQn = 60, /*!< GIRQ15 b[20] */ 135 /* reserved 61 */ 136 P80BD_0_IRQn = 62, /*!< GIRQ15 b[22] */ 137 /* reserved 63-64 */ 138 PKE_IRQn = 65, /*!< GIRQ16 b[0] */ 139 /* reserved 66 */ 140 RNG_IRQn = 67, /*!< GIRQ16 b[2] */ 141 AESH_IRQn = 68, /*!< GIRQ16 b[3] */ 142 /* reserved 69 */ 143 PECI_IRQn = 70, /*!< GIRQ17 b[0] */ 144 TACH_0_IRQn = 71, /*!< GIRQ17 b[1] */ 145 TACH_1_IRQn = 72, /*!< GIRQ17 b[2] */ 146 TACH_2_IRQn = 73, /*!< GIRQ17 b[3] */ 147 RPMFAN_0_FAIL_IRQn = 74, /*!< GIRQ17 b[20] */ 148 RPMFAN_0_STALL_IRQn = 75, /*!< GIRQ17 b[21] */ 149 RPMFAN_1_FAIL_IRQn = 76, /*!< GIRQ17 b[22] */ 150 RPMFAN_1_STALL_IRQn = 77, /*!< GIRQ17 b[23] */ 151 ADC_SNGL_IRQn = 78, /*!< GIRQ17 b[8] */ 152 ADC_RPT_IRQn = 79, /*!< GIRQ17 b[9] */ 153 RCID_0_IRQn = 80, /*!< GIRQ17 b[10] */ 154 RCID_1_IRQn = 81, /*!< GIRQ17 b[11] */ 155 RCID_2_IRQn = 82, /*!< GIRQ17 b[12] */ 156 LED_0_IRQn = 83, /*!< GIRQ17 b[13] */ 157 LED_1_IRQn = 84, /*!< GIRQ17 b[14] */ 158 LED_2_IRQn = 85, /*!< GIRQ17 b[15] */ 159 LED_3_IRQn = 86, /*!< GIRQ17 b[16] */ 160 PHOT_IRQn = 87, /*!< GIRQ17 b[17] */ 161 /* reserved 88-89 */ 162 SPIP_0_IRQn = 90, /*!< GIRQ18 b[0] */ 163 QMSPI_0_IRQn = 91, /*!< GIRQ18 b[1] */ 164 GPSPI_0_TXBE_IRQn = 92, /*!< GIRQ18 b[2] */ 165 GPSPI_0_RXBF_IRQn = 93, /*!< GIRQ18 b[3] */ 166 GPSPI_1_TXBE_IRQn = 94, /*!< GIRQ18 b[4] */ 167 GPSPI_1_RXBF_IRQn = 95, /*!< GIRQ18 b[5] */ 168 BCL_0_ERR_IRQn = 96, /*!< GIRQ18 b[7] */ 169 BCL_0_BCLR_IRQn = 97, /*!< GIRQ18 b[6] */ 170 /* reserved 98-99 */ 171 PS2_0_ACT_IRQn = 100, /*!< GIRQ18 b[10] */ 172 /* reserved 101-102 */ 173 ESPI_PC_IRQn = 103, /*!< GIRQ19 b[0] */ 174 ESPI_BM1_IRQn = 104, /*!< GIRQ19 b[1] */ 175 ESPI_BM2_IRQn = 105, /*!< GIRQ19 b[2] */ 176 ESPI_LTR_IRQn = 106, /*!< GIRQ19 b[3] */ 177 ESPI_OOB_UP_IRQn = 107, /*!< GIRQ19 b[4] */ 178 ESPI_OOB_DN_IRQn = 108, /*!< GIRQ19 b[5] */ 179 ESPI_FLASH_IRQn = 109, /*!< GIRQ19 b[6] */ 180 ESPI_RESET_IRQn = 110, /*!< GIRQ19 b[7] */ 181 RTMR_IRQn = 111, /*!< GIRQ23 b[10] */ 182 HTMR_0_IRQn = 112, /*!< GIRQ23 b[16] */ 183 HTMR_1_IRQn = 113, /*!< GIRQ23 b[17] */ 184 WK_IRQn = 114, /*!< GIRQ21 b[3] */ 185 WKSUB_IRQn = 115, /*!< GIRQ21 b[4] */ 186 WKSEC_IRQn = 116, /*!< GIRQ21 b[5] */ 187 WKSUBSEC_IRQn = 117, /*!< GIRQ21 b[6] */ 188 WKSYSPWR_IRQn = 118, /*!< GIRQ21 b[7] */ 189 RTC_IRQn = 119, /*!< GIRQ21 b[8] */ 190 RTC_ALARM_IRQn = 120, /*!< GIRQ21 b[9] */ 191 VCI_OVRD_IN_IRQn = 121, /*!< GIRQ21 b[10] */ 192 VCI_IN0_IRQn = 122, /*!< GIRQ21 b[11] */ 193 VCI_IN1_IRQn = 123, /*!< GIRQ21 b[12] */ 194 VCI_IN2_IRQn = 124, /*!< GIRQ21 b[13] */ 195 VCI_IN3_IRQn = 125, /*!< GIRQ21 b[14] */ 196 VCI_IN4_IRQn = 126, /*!< GIRQ21 b[15] */ 197 /* reserved 127-128 */ 198 PS2_0A_WAKE_IRQn = 129, /*!< GIRQ21 b[18] */ 199 PS2_0B_WAKE_IRQn = 130, /*!< GIRQ21 b[19] */ 200 /* reserved 131-134 */ 201 KEYSCAN_IRQn = 135, /*!< GIRQ21 b[25] */ 202 B16TMR_0_IRQn = 136, /*!< GIRQ23 b[0] */ 203 B16TMR_1_IRQn = 137, /*!< GIRQ23 b[1] */ 204 B16TMR_2_IRQn = 138, /*!< GIRQ23 b[2] */ 205 B16TMR_3_IRQn = 139, /*!< GIRQ23 b[3] */ 206 B32TMR_0_IRQn = 140, /*!< GIRQ23 b[4] */ 207 B32TMR_1_IRQn = 141, /*!< GIRQ23 b[5] */ 208 CTMR_0_IRQn = 142, /*!< GIRQ23 b[6] */ 209 CTMR_1_IRQn = 143, /*!< GIRQ23 b[7] */ 210 CTMR_2_IRQn = 144, /*!< GIRQ23 b[8] */ 211 CTMR_3_IRQn = 145, /*!< GIRQ23 b[9] */ 212 CCT_IRQn = 146, /*!< GIRQ18 b[20] */ 213 CCT_CAP0_IRQn = 147, /*!< GIRQ18 b[21] */ 214 CCT_CAP1_IRQn = 148, /*!< GIRQ18 b[22] */ 215 CCT_CAP2_IRQn = 149, /*!< GIRQ18 b[23] */ 216 CCT_CAP3_IRQn = 150, /*!< GIRQ18 b[24] */ 217 CCT_CAP4_IRQn = 151, /*!< GIRQ18 b[25] */ 218 CCT_CAP5_IRQn = 152, /*!< GIRQ18 b[26] */ 219 CCT_CMP0_IRQn = 153, /*!< GIRQ18 b[27] */ 220 CCT_CMP1_IRQn = 154, /*!< GIRQ18 b[28] */ 221 EEPROMC_IRQn = 155, /*!< GIRQ18 b[13] */ 222 ESPI_VWIRE_IRQn = 156, /*!< GIRQ19 b[8] */ 223 /* reserved 157 */ 224 I2C_SMB_4_IRQn = 158, /*!< GIRQ13 b[4] */ 225 TACH_3_IRQn = 159, /*!< GIRQ17 b[4] */ 226 /* reserved 160-165 */ 227 SAF_DONE_IRQn = 166, /*!< GIRQ19 b[9] */ 228 SAF_ERR_IRQn = 167, /*!< GIRQ19 b[10] */ 229 /* reserved 168 */ 230 SAF_CACHE_IRQn = 169, /*!< GIRQ19 b[11] */ 231 /* reserved 170 */ 232 WDT_0_IRQn = 171, /*!< GIRQ21 b[2] */ 233 GLUE_IRQn = 172, /*!< GIRQ21 b[26] */ 234 OTP_RDY_IRQn = 173, /*!< GIRQ20 b[3] */ 235 CLK32K_MON_IRQn = 174, /*!< GIRQ20 b[9] */ 236 ACPI_EC0_IRQn = 175, /* ACPI EC OBE and IBF combined into one */ 237 ACPI_EC1_IRQn = 176, /* No GIRQ connection. Status in ACPI blocks */ 238 ACPI_EC2_IRQn = 177, /* Code uses level bits and NVIC bits */ 239 ACPI_EC3_IRQn = 178, 240 ACPI_EC4_IRQn = 179, 241 ACPI_PM1_IRQn = 180, 242 MAX_IRQn 243 } IRQn_Type; 244 245 #include <core_cm4.h> 246 247 #include <zephyr/sys/util.h> 248 249 /* chip specific register defines */ 250 #include "reg/mec172x_defs.h" 251 #include "reg/mec172x_ecia.h" 252 #include "reg/mec172x_ecs.h" 253 #include "reg/mec172x_espi_iom.h" 254 #include "reg/mec172x_espi_saf.h" 255 #include "reg/mec172x_espi_vw.h" 256 #include "reg/mec172x_gpio.h" 257 #include "reg/mec172x_i2c_smb.h" 258 #include "reg/mec172x_p80bd.h" 259 #include "reg/mec172x_pcr.h" 260 #include "reg/mec172x_qspi.h" 261 #include "reg/mec172x_vbat.h" 262 #include "reg/mec172x_emi.h" 263 264 /* common peripheral register defines */ 265 #include "../common/reg/mec_acpi_ec.h" 266 #include "../common/reg/mec_adc.h" 267 #include "../common/reg/mec_global_cfg.h" 268 #include "../common/reg/mec_kbc.h" 269 #include "../common/reg/mec_keyscan.h" 270 #include "../common/reg/mec_peci.h" 271 #include "../common/reg/mec_ps2.h" 272 #include "../common/reg/mec_pwm.h" 273 #include "../common/reg/mec_tach.h" 274 #include "../common/reg/mec_tfdp.h" 275 #include "../common/reg/mec_timers.h" 276 #include "../common/reg/mec_uart.h" 277 #include "../common/reg/mec_vci.h" 278 #include "../common/reg/mec_wdt.h" 279 #include "../common/reg/mec_gpio.h" 280 281 /* common SoC API */ 282 #include "../common/soc_dt.h" 283 #include "../common/soc_gpio.h" 284 #include "../common/soc_pcr.h" 285 #include "../common/soc_pins.h" 286 #include "../common/soc_espi_channels.h" 287 #include "../common/soc_i2c.h" 288 289 /* MEC172x SAF V2 */ 290 #include "soc_espi_saf_v2.h" 291 292 #endif 293 294 #endif 295
