Lines Matching +full:revision +full:- +full:reg
7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
19 #include <zephyr/dt-bindings/adc/adc.h>
20 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
21 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
22 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
28 zephyr,flash-controller = &flash;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-m7";
38 reg = <0>;
39 #address-cells = <1>;
40 #size-cells = <1>;
43 compatible = "arm,armv7m-mpu";
44 reg = <0xe000ed90 0x40>;
50 compatible = "zephyr,memory-region";
51 reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */
52 zephyr,memory-region = "EXTMEM";
53 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>;
57 #address-cells = <1>;
58 #size-cells = <0>;
60 clk_hse: clk-hse {
61 #clock-cells = <0>;
62 compatible = "st,stm32-hse-clock";
66 clk_hsi: clk-hsi {
67 #clock-cells = <0>;
68 compatible = "st,stm32h7-hsi-clock";
69 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
70 clock-frequency = <DT_FREQ_M(64)>;
74 clk_hsi48: clk-hsi48 {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <DT_FREQ_M(48)>;
81 clk_csi: clk-csi {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <DT_FREQ_M(4)>;
88 clk_lse: clk-lse {
89 #clock-cells = <0>;
90 compatible = "st,stm32-lse-clock";
91 clock-frequency = <32768>;
92 driving-capability = <0>;
96 clk_lsi: clk-lsi {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <DT_FREQ_K(32)>;
104 #clock-cells = <0>;
105 compatible = "st,stm32h7-pll-clock";
106 reg = <0>;
111 #clock-cells = <0>;
112 compatible = "st,stm32h7-pll-clock";
113 reg = <1>;
118 #clock-cells = <0>;
119 compatible = "st,stm32h7-pll-clock";
120 reg = <2>;
125 #clock-cells = <0>;
126 compatible = "st,stm32-clock-mux";
133 compatible = "st,stm32-clock-mco";
138 compatible = "st,stm32-clock-mco";
144 flash: flash-controller@52002000 {
145 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller";
146 reg = <0x52002000 0x400>;
149 #address-cells = <1>;
150 #size-cells = <1>;
154 compatible = "st,stm32h7-rcc";
155 #clock-cells = <2>;
156 reg = <0x58024400 0x400>;
158 rctl: reset-controller {
159 compatible = "st,stm32-rcc-rctl";
160 #reset-cells = <1>;
164 exti: interrupt-controller@58000000 {
165 compatible = "st,stm32-exti";
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 #address-cells = <1>;
169 reg = <0x58000000 0x400>;
170 num-lines = <16>;
173 interrupt-names = "line0", "line1", "line2", "line3",
174 "line4", "line5-9", "line10-15";
175 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
179 pinctrl: pin-controller@58020000 {
180 compatible = "st,stm32-pinctrl";
181 #address-cells = <1>;
182 #size-cells = <1>;
183 reg = <0x58020000 0x2400>;
186 compatible = "st,stm32-gpio";
187 gpio-controller;
188 #gpio-cells = <2>;
189 reg = <0x58020000 0x400>;
194 compatible = "st,stm32-gpio";
195 gpio-controller;
196 #gpio-cells = <2>;
197 reg = <0x58020400 0x400>;
202 compatible = "st,stm32-gpio";
203 gpio-controller;
204 #gpio-cells = <2>;
205 reg = <0x58020800 0x400>;
210 compatible = "st,stm32-gpio";
211 gpio-controller;
212 #gpio-cells = <2>;
213 reg = <0x58020C00 0x400>;
218 compatible = "st,stm32-gpio";
219 gpio-controller;
220 #gpio-cells = <2>;
221 reg = <0x58021000 0x400>;
226 compatible = "st,stm32-gpio";
227 gpio-controller;
228 #gpio-cells = <2>;
229 reg = <0x58021400 0x400>;
234 compatible = "st,stm32-gpio";
235 gpio-controller;
236 #gpio-cells = <2>;
237 reg = <0x58021800 0x400>;
242 compatible = "st,stm32-gpio";
243 gpio-controller;
244 #gpio-cells = <2>;
245 reg = <0x58021C00 0x400>;
250 compatible = "st,stm32-gpio";
251 gpio-controller;
252 #gpio-cells = <2>;
253 reg = <0x58022000 0x400>;
258 compatible = "st,stm32-gpio";
259 gpio-controller;
260 #gpio-cells = <2>;
261 reg = <0x58022400 0x400>;
266 compatible = "st,stm32-gpio";
267 gpio-controller;
268 #gpio-cells = <2>;
269 reg = <0x58022800 0x400>;
275 compatible = "st,stm32-watchdog";
276 reg = <0x58004800 0x400>;
281 compatible = "st,stm32-window-watchdog";
282 reg = <0x50003000 0x1000>;
289 compatible = "st,stm32-usart", "st,stm32-uart";
290 reg = <0x40011000 0x400>;
297 compatible = "st,stm32-usart", "st,stm32-uart";
298 reg = <0x40004400 0x400>;
305 compatible = "st,stm32-usart", "st,stm32-uart";
306 reg = <0x40004800 0x400>;
313 compatible ="st,stm32-uart";
314 reg = <0x40004c00 0x400>;
321 compatible = "st,stm32-uart";
322 reg = <0x40005000 0x400>;
329 compatible = "st,stm32-usart", "st,stm32-uart";
330 reg = <0x40011400 0x400>;
337 compatible = "st,stm32-uart";
338 reg = <0x40007800 0x400>;
345 compatible = "st,stm32-uart";
346 reg = <0x40007c00 0x400>;
354 compatible = "st,stm32-lpuart", "st,stm32-uart";
355 reg = <0x58000c00 0x400>;
363 compatible = "st,stm32-rtc";
364 reg = <0x58004000 0x400>;
368 alarms-count = <2>;
369 alrm-exti-line = <17>;
374 compatible = "st,stm32-i2c-v2";
375 clock-frequency = <I2C_BITRATE_STANDARD>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 reg = <0x40005400 0x400>;
381 interrupt-names = "event", "error";
386 compatible = "st,stm32-i2c-v2";
387 clock-frequency = <I2C_BITRATE_STANDARD>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390 reg = <0x40005800 0x400>;
393 interrupt-names = "event", "error";
398 compatible = "st,stm32-i2c-v2";
399 clock-frequency = <I2C_BITRATE_STANDARD>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 reg = <0x40005c00 0x400>;
405 interrupt-names = "event", "error";
410 compatible = "st,stm32-i2c-v2";
411 clock-frequency = <I2C_BITRATE_STANDARD>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 reg = <0x58001c00 0x400>;
417 interrupt-names = "event", "error";
422 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 reg = <0x40013000 0x400>;
433 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
434 #address-cells = <1>;
435 #size-cells = <0>;
436 reg = <0x40003800 0x400>;
444 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 reg = <0x40003c00 0x400>;
455 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <0x40013400 0x400>;
465 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 reg = <0x40015000 0x400>;
475 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <0x58001400 0x400>;
485 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 reg = <0x40013000 0x400>;
493 dma-names = "tx", "rx";
499 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
500 #address-cells = <1>;
501 #size-cells = <0>;
502 reg = <0x40003800 0x400>;
507 dma-names = "tx", "rx";
513 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 reg = <0x40003c00 0x400>;
521 dma-names = "tx", "rx";
527 compatible = "st,stm32h7-fdcan";
528 reg = <0x4000a000 0x400>, <0x4000ac00 0x350>;
529 reg-names = "m_can", "message_ram";
532 interrupt-names = "int0", "int1", "calib";
533 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
538 compatible = "st,stm32h7-fdcan";
539 reg = <0x4000a400 0x400>, <0x4000ac00 0x6a0>;
540 reg-names = "m_can", "message_ram";
543 interrupt-names = "int0", "int1", "calib";
544 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
549 compatible = "st,stm32-timers";
550 reg = <0x40010000 0x400>;
554 interrupt-names = "brk", "up", "trgcom", "cc";
559 compatible = "st,stm32-pwm";
561 #pwm-cells = <3>;
566 compatible = "st,stm32-timers";
567 reg = <0x40000000 0x400>;
571 interrupt-names = "global";
576 compatible = "st,stm32-pwm";
578 #pwm-cells = <3>;
582 compatible = "st,stm32-counter";
588 compatible = "st,stm32-timers";
589 reg = <0x40000400 0x400>;
593 interrupt-names = "global";
598 compatible = "st,stm32-pwm";
600 #pwm-cells = <3>;
604 compatible = "st,stm32-counter";
610 compatible = "st,stm32-timers";
611 reg = <0x40000800 0x400>;
615 interrupt-names = "global";
620 compatible = "st,stm32-pwm";
622 #pwm-cells = <3>;
626 compatible = "st,stm32-counter";
632 compatible = "st,stm32-timers";
633 reg = <0x40000c00 0x400>;
637 interrupt-names = "global";
642 compatible = "st,stm32-pwm";
644 #pwm-cells = <3>;
648 compatible = "st,stm32-counter";
654 compatible = "st,stm32-timers";
655 reg = <0x40001000 0x400>;
659 interrupt-names = "global";
664 compatible = "st,stm32-counter";
670 compatible = "st,stm32-timers";
671 reg = <0x40001400 0x400>;
675 interrupt-names = "global";
680 compatible = "st,stm32-counter";
686 compatible = "st,stm32-timers";
687 reg = <0x40010400 0x400>;
691 interrupt-names = "brk", "up", "trgcom", "cc";
696 compatible = "st,stm32-pwm";
698 #pwm-cells = <3>;
703 compatible = "st,stm32-timers";
704 reg = <0x40001800 0x400>;
708 interrupt-names = "global";
713 compatible = "st,stm32-pwm";
715 #pwm-cells = <3>;
719 compatible = "st,stm32-counter";
725 compatible = "st,stm32-timers";
726 reg = <0x40001c00 0x400>;
730 interrupt-names = "global";
735 compatible = "st,stm32-pwm";
737 #pwm-cells = <3>;
741 compatible = "st,stm32-counter";
747 compatible = "st,stm32-timers";
748 reg = <0x40002000 0x400>;
752 interrupt-names = "global";
757 compatible = "st,stm32-pwm";
759 #pwm-cells = <3>;
763 compatible = "st,stm32-counter";
769 compatible = "st,stm32-timers";
770 reg = <0x40014000 0x400>;
774 interrupt-names = "global";
779 compatible = "st,stm32-pwm";
781 #pwm-cells = <3>;
785 compatible = "st,stm32-counter";
791 compatible = "st,stm32-timers";
792 reg = <0x40014400 0x400>;
796 interrupt-names = "global";
801 compatible = "st,stm32-pwm";
803 #pwm-cells = <3>;
807 compatible = "st,stm32-counter";
813 compatible = "st,stm32-timers";
814 reg = <0x40014800 0x400>;
818 interrupt-names = "global";
823 compatible = "st,stm32-pwm";
825 #pwm-cells = <3>;
829 compatible = "st,stm32-counter";
835 compatible = "st,stm32-lptim";
837 #address-cells = <1>;
838 #size-cells = <0>;
839 reg = <0x40002400 0x400>;
841 interrupt-names = "wakeup";
846 * For devices STM32H742, H743, H750 & H753, revision Y only,
853 compatible = "st,stm32-adc";
854 reg = <0x40022000 0x400>;
858 #io-channel-cells = <1>;
864 sampling-times = <2 3 9 17 33 65 388 811>;
865 st,adc-sequencer = "FULLY_CONFIGURABLE";
866 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
870 compatible = "st,stm32-adc";
871 reg = <0x40022100 0x400>;
875 #io-channel-cells = <1>;
881 sampling-times = <2 3 9 17 33 65 388 811>;
882 st,adc-sequencer = "FULLY_CONFIGURABLE";
883 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
888 compatible = "st,stm32-adc";
889 reg = <0x40022300 0x400>;
893 #io-channel-cells = <1>;
899 sampling-times = <2 3 9 17 33 65 388 811>;
900 st,adc-sequencer = "FULLY_CONFIGURABLE";
901 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
905 compatible = "st,stm32-adc";
906 reg = <0x58026000 0x400>;
910 #io-channel-cells = <1>;
916 sampling-times = <2 3 9 17 33 65 388 811>;
917 st,adc-sequencer = "FULLY_CONFIGURABLE";
918 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
922 compatible = "st,stm32-dac";
923 reg = <0x40007400 0x400>;
926 #io-channel-cells = <1>;
930 compatible = "st,stm32-dma-v1";
931 #dma-cells = <4>;
932 reg = <0x40020000 0x400>;
937 dma-offset = <0>;
938 dma-requests = <8>;
943 compatible = "st,stm32-dma-v1";
944 #dma-cells = <4>;
945 reg = <0x40020400 0x400>;
950 dma-offset = <8>;
951 dma-requests = <8>;
956 compatible = "st,stm32-bdma";
957 #dma-cells = <4>;
958 reg = <0x58025400 0x400>;
963 dma-offset = <0>;
964 dma-requests = <8>;
969 compatible = "st,stm32-dmamux";
970 #dma-cells = <3>;
971 reg = <0x40020800 0x400>;
975 dma-channels = <16>;
976 dma-generators = <8>;
979 * dma-requests is different among h7 socs,
985 compatible = "st,stm32-dmamux";
986 #dma-cells = <3>;
987 reg = <0x58025800 0x400>;
991 dma-channels = <8>;
992 dma-generators = <8>;
995 * dma-requests is different among h7 socs,
1001 compatible = "st,stm32-rng";
1002 reg = <0x48021800 0x400>;
1009 compatible = "st,stm32-sdmmc";
1010 reg = <0x52007000 0x400>;
1019 compatible = "st,stm32-sdmmc";
1020 reg = <0x48022400 0x400>;
1029 compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
1030 reg = <0x40028000 0x8000>;
1032 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
1039 compatible = "st,stm32-mdio";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1046 fmc: memory-controller@52004000 {
1047 compatible = "st,stm32h7-fmc";
1048 reg = <0x52004000 0x400>;
1053 compatible = "st,stm32-fmc-sdram";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1061 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
1062 reg = <0x38800000 DT_SIZE_K(4)>;
1064 zephyr,memory-region = "BACKUP_SRAM";
1069 compatible = "st,stm32-qspi";
1070 #address-cells = <0x1>;
1071 #size-cells = <0x0>;
1072 reg = <0x52005000 0x34>;
1079 compatible = "st,stm32-dcmi";
1080 reg = <0x48020000 0x400>;
1082 interrupt-names = "dcmi";
1089 compatible = "st,stm32-temp-cal";
1090 ts-cal1-addr = <0x1FF1E820>;
1091 ts-cal2-addr = <0x1FF1E840>;
1092 ts-cal1-temp = <30>;
1093 ts-cal2-temp = <110>;
1094 ts-cal-vrefanalog = <3300>;
1095 ts-cal-resolution = <16>;
1096 io-channels = <&adc3 18>;
1101 compatible = "st,stm32-vbat";
1107 compatible = "st,stm32-vref";
1108 vrefint-cal-addr = <0x1FF1E860>;
1109 vrefint-cal-mv = <3300>;
1114 compatible = "st,stm32-smbus";
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1122 compatible = "st,stm32-smbus";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1130 compatible = "st,stm32-smbus";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1138 compatible = "st,stm32-smbus";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1147 arm,num-irq-priority-bits = <4>;