1# Copyright (c) 2020, NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: NXP MCUX EDMA controller
5
6compatible: "nxp,mcux-edma"
7
8include: dma-controller.yaml
9
10properties:
11  reg:
12    required: true
13    description: |
14      Specifies base physical address(s) and size of DMA and respective DMAMUX register(s)
15      that routes DMA sources
16
17  interrupts:
18    required: true
19
20  dma-channels:
21    required: true
22
23  dma-requests:
24    required: true
25
26  dmamux-reg-offset:
27    type: int
28    default: 0
29    description:
30      The offset value for obtaining DMAMUX register index from DMAMUX channel.
31      Default value means DMAMUX channel is identical with DMAMUX register index
32
33  channel-gap:
34    type: array
35    description: |
36      On some platforms, there may be a gap in the channels and
37      this array specifies the start and end of a single gap
38
39  nxp,mem2mem:
40    type: boolean
41    description: If the DMA controller supports memory to memory transfer
42
43  nxp,a_on:
44    type: boolean
45    description: If the DMA controller supports always on
46
47  irq-shared-offset:
48    type: int
49    default: 0
50    description: |
51      Describes an offset between two channels share the same interrupt entry.
52      Default value means each channel has separate interrupt entry.
53
54  no-error-irq:
55    type: boolean
56    description: |
57      If the SoCs don't have a separate interrupt id for error IRQ.
58
59  nxp,version:
60    type: int
61    enum:
62      - 2
63      - 3
64      - 4
65    description: |
66      eDMA IP revision number.
67
68  "#dma-cells":
69    type: int
70    required: true
71    description: Number of items to expect in a DMAMUX specifier
72
73# - #dma-cells : Must be <2>.
74#  The 1st cell specifies the DMA channel which will be used
75#  The 2nd cell specifies the request source (slot) ID.
76#    See the SoC's reference manual for all the supported request sources.
77
78dma-cells:
79  - mux
80  - source
81