Lines Matching +full:revision +full:- +full:reg
4 * SPDX-License-Identifier: Apache-2.0
14 * eight regions. Zephyr has an in-tree CMSIS header located in the arch
16 * from hal_cmsis based on the k-config CPU selection.
17 * The Zephyr in-tree header does not provide all the symbols ARM CMSIS
19 * MPU present to 0. We define these two symbols here based on our k-config
20 * selections. NOTE: Zephyr in-tree CMSIS defines the Cortex-M4 hardware
21 * revision to 0. At this time ARM CMSIS does not appear to use the hardware
22 * revision in any macros.
27 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
33 #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
34 #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
37 /** @brief ARM Cortex-M4 NVIC Interrupt Numbers
39 * negative numbers [-15, -1]. Lower numerical value indicates higher
41 * -15 = Reset Vector invoked on POR or any CPU reset.
42 * -14 = NMI
43 * -13 = Hard Fault. At POR or CPU reset all faults map to Hard Fault.
44 * -12 = Memory Management Fault. If enabled Hard Faults caused by access
46 * -11 = Bus Fault. If enabled pre-fetch, AHB access faults.
47 * -10 = Usage Fault. If enabled Undefined instructions, illegal state
48 * transition (Thumb -> ARM mode), unaligned, etc.
49 * -9 through -6 are not implemented (reserved).
50 * -5 System call via SVC instruction.
51 * -4 Debug Monitor.
52 * -3 not implemented (reserved).
53 * -2 PendSV for system service.
54 * -1 SysTick NVIC system timer.
58 /* ========== ARM Cortex-M4 Specific Interrupt Numbers ============ */
60 Reset_IRQn = -15, /*!< POR/CPU Reset Vector */
61 NonMaskableInt_IRQn = -14, /*!< NMI */
62 HardFault_IRQn = -13, /*!< Hard Faults */
63 MemoryManagement_IRQn = -12, /*!< Memory Management faults */
64 BusFault_IRQn = -11, /*!< Bus Access faults */
65 UsageFault_IRQn = -10, /*!< Usage/instruction faults */
66 SVCall_IRQn = -5, /*!< SVC */
67 DebugMonitor_IRQn = -4, /*!< Debug Monitor */
68 PendSV_IRQn = -2, /*!< PendSV */
69 SysTick_IRQn = -1, /*!< SysTick */
73 GIRQ08_IRQn = 0, /*!< GPIO 0140 - 0176 */
74 GIRQ09_IRQn = 1, /*!< GPIO 0100 - 0136 */
75 GIRQ10_IRQn = 2, /*!< GPIO 0040 - 0076 */
76 GIRQ11_IRQn = 3, /*!< GPIO 0000 - 0036 */
77 GIRQ12_IRQn = 4, /*!< GPIO 0200 - 0236 */
91 GIRQ26_IRQn = 17, /*!< GPIO 0240 - 0276 */
92 /* Reserved 18-19 */
93 /* GIRQ's 8 - 12, 24 - 26 no direct connections */
137 /* reserved 63-64 */
161 /* reserved 88-89 */
170 /* reserved 98-99 */
172 /* reserved 101-102 */
197 /* reserved 127-128 */
200 /* reserved 131-134 */
226 /* reserved 160-165 */
250 #include "reg/mec172x_defs.h"
251 #include "reg/mec172x_ecia.h"
252 #include "reg/mec172x_ecs.h"
253 #include "reg/mec172x_espi_iom.h"
254 #include "reg/mec172x_espi_saf.h"
255 #include "reg/mec172x_espi_vw.h"
256 #include "reg/mec172x_gpio.h"
257 #include "reg/mec172x_i2c_smb.h"
258 #include "reg/mec172x_p80bd.h"
259 #include "reg/mec172x_pcr.h"
260 #include "reg/mec172x_qspi.h"
261 #include "reg/mec172x_vbat.h"
262 #include "reg/mec172x_emi.h"
265 #include "../common/reg/mec_acpi_ec.h"
266 #include "../common/reg/mec_adc.h"
267 #include "../common/reg/mec_global_cfg.h"
268 #include "../common/reg/mec_kbc.h"
269 #include "../common/reg/mec_keyscan.h"
270 #include "../common/reg/mec_peci.h"
271 #include "../common/reg/mec_ps2.h"
272 #include "../common/reg/mec_pwm.h"
273 #include "../common/reg/mec_tach.h"
274 #include "../common/reg/mec_tfdp.h"
275 #include "../common/reg/mec_timers.h"
276 #include "../common/reg/mec_uart.h"
277 #include "../common/reg/mec_vci.h"
278 #include "../common/reg/mec_wdt.h"
279 #include "../common/reg/mec_gpio.h"