4  * SPDX-License-Identifier: Apache-2.0
73 	const struct adc_sam0_cfg *const cfg = dev->config;  in adc_sam0_acquisition_to_clocks()
79 			return -EINVAL;  in adc_sam0_acquisition_to_clocks()
82 		return (int)ADC_ACQ_TIME_VALUE(acquisition_time) - 1;  in adc_sam0_acquisition_to_clocks()
92 		return -EINVAL;  in adc_sam0_acquisition_to_clocks()
97 	 * sample_length = sample_time * (2/clk_adc) - 1,  in adc_sam0_acquisition_to_clocks()
101 	scaled_acq += cfg->freq / 2U;  in adc_sam0_acquisition_to_clocks()
102 	scaled_acq /= cfg->freq;  in adc_sam0_acquisition_to_clocks()
107 	scaled_acq -= 1U;  in adc_sam0_acquisition_to_clocks()
109 		return -EINVAL;  in adc_sam0_acquisition_to_clocks()
118 	const struct adc_sam0_cfg *const cfg = dev->config;  in adc_sam0_channel_setup()
119 	Adc *const adc = cfg->regs;  in adc_sam0_channel_setup()
123 	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {  in adc_sam0_channel_setup()
125 							channel_cfg->acquisition_time);  in adc_sam0_channel_setup()
134 	adc->SAMPCTRL.reg = sampctrl;  in adc_sam0_channel_setup()
139 	switch (channel_cfg->reference) {  in adc_sam0_channel_setup()
163 		return -EINVAL;  in adc_sam0_channel_setup()
165 	if (adc->REFCTRL.reg != refctrl) {  in adc_sam0_channel_setup()
167 		adc->CTRLA.bit.ENABLE = 0;  in adc_sam0_channel_setup()
170 		adc->REFCTRL.reg = refctrl;  in adc_sam0_channel_setup()
173 		adc->CTRLA.bit.ENABLE = 1;  in adc_sam0_channel_setup()
177 		struct adc_sam0_data *data = dev->data;  in adc_sam0_channel_setup()
179 		data->reference_changed = 1;  in adc_sam0_channel_setup()
186 	switch (channel_cfg->gain) {  in adc_sam0_channel_setup()
219 		return -EINVAL;  in adc_sam0_channel_setup()
222 	inputctrl |= ADC_INPUTCTRL_MUXPOS(channel_cfg->input_positive);  in adc_sam0_channel_setup()
223 	if (channel_cfg->differential) {  in adc_sam0_channel_setup()
224 		inputctrl |= ADC_INPUTCTRL_MUXNEG(channel_cfg->input_negative);  in adc_sam0_channel_setup()
234 	adc->INPUTCTRL.reg = inputctrl;  in adc_sam0_channel_setup()
238 	switch (channel_cfg->input_positive) {  in adc_sam0_channel_setup()
267 	const struct adc_sam0_cfg *const cfg = dev->config;  in adc_sam0_start_conversion()
268 	Adc *const adc = cfg->regs;  in adc_sam0_start_conversion()
272 	adc->SWTRIG.reg = ADC_SWTRIG_START;  in adc_sam0_start_conversion()
285 	adc_sam0_start_conversion(data->dev);  in adc_context_start_sampling()
295 		data->buffer = data->repeat_buffer;  in adc_context_update_buffer_pointer()
305 	if (sequence->options) {  in check_buffer_size()
306 		needed_buffer_size *= (1U + sequence->options->extra_samplings);  in check_buffer_size()
309 	if (sequence->buffer_size < needed_buffer_size) {  in check_buffer_size()
311 			sequence->buffer_size, needed_buffer_size);  in check_buffer_size()
312 		return -ENOMEM;  in check_buffer_size()
320 	const struct adc_sam0_cfg *const cfg = dev->config;  in start_read()
321 	struct adc_sam0_data *data = dev->data;  in start_read()
322 	Adc *const adc = cfg->regs;  in start_read()
325 	if (sequence->oversampling > 10U) {  in start_read()
327 		return -EINVAL;  in start_read()
330 	adc->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM(sequence->oversampling);  in start_read()
338 	if (sequence->oversampling > 4U && DSU->DID.bit.REVISION < 3) {  in start_read()
339 		adc->AVGCTRL.bit.ADJRES = sequence->oversampling - 4U;  in start_read()
343 	switch (sequence->resolution) {  in start_read()
345 		if (sequence->oversampling) {  in start_read()
347 			return -EINVAL;  in start_read()
353 		if (sequence->oversampling) {  in start_read()
355 			return -EINVAL;  in start_read()
361 		if (sequence->oversampling) {  in start_read()
369 			sequence->resolution);  in start_read()
370 		return -EINVAL;  in start_read()
375 	if ((sequence->channels == 0)  in start_read()
376 		|| ((sequence->channels & (sequence->channels - 1)) != 0)) {  in start_read()
381 		 * might be sensible, this will likely break users before this revision  in start_read()
385 		return -ENOTSUP;  in start_read()
393 	data->buffer = sequence->buffer;  in start_read()
394 	data->repeat_buffer = sequence->buffer;  in start_read()
401 	adc_context_start_read(&data->ctx, sequence);  in start_read()
403 	error = adc_context_wait_for_completion(&data->ctx);  in start_read()
410 	struct adc_sam0_data *data = dev->data;  in adc_sam0_read()
413 	adc_context_lock(&data->ctx, false, NULL);  in adc_sam0_read()
415 	adc_context_release(&data->ctx, error);  in adc_sam0_read()
422 	struct adc_sam0_data *data = dev->data;  in adc_sam0_isr()
423 	const struct adc_sam0_cfg *const cfg = dev->config;  in adc_sam0_isr()
424 	Adc *const adc = cfg->regs;  in adc_sam0_isr()
427 	adc->INTFLAG.reg = ADC_INTFLAG_MASK;  in adc_sam0_isr()
429 	result = (uint16_t)(adc->RESULT.reg);  in adc_sam0_isr()
432 	if (data->reference_changed) {  in adc_sam0_isr()
433 		data->reference_changed = 0;  in adc_sam0_isr()
441 	*data->buffer++ = result;  in adc_sam0_isr()
442 	adc_context_on_sampling_done(&data->ctx, dev);  in adc_sam0_isr()
447 	const struct adc_sam0_cfg *const cfg = dev->config;  in adc_sam0_init()
448 	struct adc_sam0_data *data = dev->data;  in adc_sam0_init()
449 	Adc *const adc = cfg->regs;  in adc_sam0_init()
453 	GCLK->PCHCTRL[cfg->gclk_id].reg = cfg->gclk_mask | GCLK_PCHCTRL_CHEN;  in adc_sam0_init()
455 	MCLK_ADC |= cfg->mclk_mask;  in adc_sam0_init()
457 	PM->APBCMASK.bit.ADC_ = 1;  in adc_sam0_init()
459 	GCLK->CLKCTRL.reg = cfg->gclk | GCLK_CLKCTRL_CLKEN;  in adc_sam0_init()
462 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);  in adc_sam0_init()
467 	ADC_PRESCALER(adc) = cfg->prescaler;  in adc_sam0_init()
470 	adc->INTENCLR.reg = ADC_INTENCLR_MASK;  in adc_sam0_init()
471 	adc->INTFLAG.reg = ADC_INTFLAG_MASK;  in adc_sam0_init()
473 	cfg->config_func(dev);  in adc_sam0_init()
475 	adc->INTENSET.reg = ADC_INTENSET_RESRDY;  in adc_sam0_init()
477 	data->dev = dev;  in adc_sam0_init()
479 	data->reference_changed = 1;  in adc_sam0_init()
482 	adc->CTRLA.bit.ENABLE = 1;  in adc_sam0_init()
485 	adc_context_unlock_unconditionally(&data->ctx);  in adc_sam0_init()
495 	struct adc_sam0_data *data = dev->data;  in adc_sam0_read_async()
498 	adc_context_lock(&data->ctx, true, async);  in adc_sam0_read_async()
500 	adc_context_release(&data->ctx, error);  in adc_sam0_read_async()
528 	const struct adc_sam0_cfg *const cfg = dev->config;		\
529 	Adc * const adc = cfg->regs;					\
530 	adc->CALIB.reg = ADC_SAM0_BIASCOMP(n)				\
545 	const struct adc_sam0_cfg *const cfg = dev->config;		\
546 	Adc * const adc = cfg->regs;					\
556 	adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) |			\