Lines Matching +full:revision +full:- +full:reg
4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx4/npcx4-alts-map.dtsi"
10 #include "npcx4/npcx4-miwus-wui-map.dtsi"
12 #include "npcx4/npcx4-miwus-int-map.dtsi"
14 #include "npcx4/npcx4-espi-vws-map.dtsi"
15 /* npcx4 series low-voltage io controls mapping table */
16 #include "npcx4/npcx4-lvol-ctrl-map.dtsi"
18 #include "zephyr/dt-bindings/reset/npcx4_reset.h"
26 cpu-power-states = <&suspend_to_idle0>;
29 power-states {
30 suspend_to_idle0: suspend-to-idle0 {
31 compatible = "zephyr,power-state";
32 power-state-name = "suspend-to-idle";
33 substate-id = <0>;
34 min-residency-us = <1000>;
39 def-io-conf-list {
79 compatible = "nuvoton,npcx4", "nuvoton,npcx", "simple-bus";
87 bbram: bb-ram@400af001 {
88 compatible = "nuvoton,npcx-bbram";
89 reg = <0x400af001 0x7F
91 reg-names = "memory", "status";
96 compatible = "nuvoton,npcx-itim-timer";
97 reg = <0x400b0000 0x2000
99 reg-names = "evt_itim", "sys_itim";
106 compatible = "nuvoton,npcx-uart";
108 reg = <0x400E0000 0x2000 0x40011100 0x100>;
113 uart-rx = <&wui_cr_sin1>;
118 compatible = "nuvoton,npcx-uart";
120 reg = <0x400E2000 0x2000 0x40011200 0x100>;
123 uart-rx = <&wui_cr_sin2>;
128 compatible = "nuvoton,npcx-uart";
130 reg = <0x400E4000 0x2000 0x40011300 0x100>;
135 uart-rx = <&wui_cr_sin3>;
140 compatible = "nuvoton,npcx-uart";
142 reg = <0x400E6000 0x2000 0x40011400 0x100>;
147 uart-rx = <&wui_cr_sin4>;
152 pcc: clock-controller@4000d000 {
153 clock-frequency = <DT_FREQ_M(120)>; /* OFMCLK runs at 120MHz */
154 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */
155 apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */
156 apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */
157 apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */
158 apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */
159 ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */
160 pwdwn-ctl-val = <0xfb
170 /* Wake-up input source mapping for GPIOs in npcx4 series */
172 wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
175 lvol-maps = <&lvol_io00 &lvol_io01 &lvol_io02 &lvol_io03
180 wui-maps = <&wui_io10 &wui_io11 &wui_io12 &wui_io13
183 lvol-maps = <&lvol_io10 &lvol_io11 &lvol_none &lvol_io13
188 wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
191 lvol-maps = <&lvol_io20 &lvol_io21 &lvol_io22 &lvol_io23
196 wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
199 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
204 wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
207 lvol-maps = <&lvol_io40 &lvol_io41 &lvol_io42 &lvol_io43
212 wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
215 lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
220 wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
223 lvol-maps = <&lvol_io60 &lvol_io61 &lvol_io62 &lvol_io63
228 wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
231 lvol-maps = <&lvol_io70 &lvol_none &lvol_io72 &lvol_io73
236 wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
239 lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_io83
244 wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
247 lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
252 wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
255 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
260 wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
263 lvol-maps = <&lvol_none &lvol_iob1 &lvol_iob2 &lvol_iob3
268 wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
271 lvol-maps = <&lvol_ioc0 &lvol_ioc1 &lvol_ioc2 &lvol_ioc3
276 wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
279 lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_iod2 &lvol_iod3
284 wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
287 lvol-maps = <&lvol_ioe0 &lvol_ioe1 &lvol_ioe2 &lvol_ioe3
292 wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
295 lvol-maps = <&lvol_iof0 &lvol_iof1 &lvol_iof2 &lvol_iof3
301 channel-count = <26>;
302 threshold-count = <6>;
307 compatible = "nuvoton,npcx-adc";
308 #io-channel-cells = <1>;
309 reg = <0x400d5000 0x2000>;
312 vref-mv = <3300>;
313 channel-count = <26>;
314 threshold-count = <6>;
325 compatible = "nuvoton,npcx-fiu-qspi";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <0x40021000 0x1000>;
333 compatible = "nuvoton,npcx-sha";
334 reg = <0x148 0x4c>;
335 context-buffer-size = <240>;
340 compatible = "nuvoton,npcx-shi-enhanced";
341 reg = <0x4000f000 0x120>;
345 buffer-rx-size = <128>;
346 buffer-tx-size = <128>;
347 shi-cs-wui =<&wui_io53>;
351 rx-plsize = <64>;
352 tx-plsize = <64>;
355 compatible = "nuvoton,npcx-espi-taf";
356 reg = <0x4000a000 0x2000>;
361 rctl: reset-controller@400c3100 {
362 compatible = "nuvoton,npcx-rst";
363 reg = <0x400c3100 0x14>;
364 #reset-cells = <1>;
369 compatible = "nuvoton,npcx-i3c";
371 /* reg[0]: I3C_1 register, reg[1]: MDMA5 register */
372 reg-names = "i3c1", "mdma5";
373 reg = <0x400f0000 0x2000>,
383 clock-names = "mclkd", "apb4", "mdma5";
389 #address-cells = <3>;
390 #size-cells = <0>;
391 instance-id = <0x00>;
395 compatible = "nuvoton,npcx-i3c";
397 /* reg[0]: I3C_2 register, reg[1]: MDMA6 register */
398 reg-names = "i3c2", "mdma6";
399 reg = <0x400f2000 0x2000>,
409 clock-names = "mclkd", "apb4", "mdma6";
415 #address-cells = <3>;
416 #size-cells = <0>;
417 instance-id = <0x10>;
421 compatible = "nuvoton,npcx-i3c";
423 /* reg[0]: I3C_3 register, reg[1]: MDMA7 register */
424 reg-names = "i3c1", "mdma7";
425 reg = <0x400f4000 0x2000>,
435 clock-names = "mclkd", "apb4", "mdma7";
441 #address-cells = <3>;
442 #size-cells = <0>;
443 instance-id = <0x20>;
447 soc-if {
449 compatible = "nuvoton,npcx-i2c-port";
450 #address-cells = <1>;
451 #size-cells = <0>;
458 compatible = "nuvoton,npcx-i2c-port";
459 #address-cells = <1>;
460 #size-cells = <0>;
467 soc-id {
468 family-id = <0x23>;
469 chip-id = <0x0a>;
470 revision-reg = <0x0000FFFC 4>;