Lines Matching +full:revision +full:- +full:reg
4 * SPDX-License-Identifier: Apache-2.0
26 * SERCOM revision 0x500
96 while ((usart->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_MASK) != 0) { in wait_synchronization()
100 while ((usart->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
118 return -ERANGE; in uart_sam0_set_baudrate()
121 baud = 65536 - (uint16_t)tmp; in uart_sam0_set_baudrate()
122 usart->BAUD.reg = baud; in uart_sam0_set_baudrate()
140 const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg; in uart_sam0_dma_tx_done()
142 SercomUsart * const regs = cfg->regs; in uart_sam0_dma_tx_done()
144 regs->INTENSET.reg = SERCOM_USART_INTENSET_TXC; in uart_sam0_dma_tx_done()
149 const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg; in uart_sam0_tx_halt()
151 size_t tx_active = dev_data->tx_len; in uart_sam0_tx_halt()
157 .buf = dev_data->tx_buf, in uart_sam0_tx_halt()
162 dev_data->tx_buf = NULL; in uart_sam0_tx_halt()
163 dev_data->tx_len = 0U; in uart_sam0_tx_halt()
165 dma_stop(cfg->dma_dev, cfg->tx_dma_channel); in uart_sam0_tx_halt()
169 if (dma_get_status(cfg->dma_dev, cfg->tx_dma_channel, &st) == 0) { in uart_sam0_tx_halt()
170 evt.data.tx.len = tx_active - st.pending_length; in uart_sam0_tx_halt()
174 if (dev_data->async_cb) { in uart_sam0_tx_halt()
175 dev_data->async_cb(dev_data->dev, in uart_sam0_tx_halt()
176 &evt, dev_data->async_cb_data); in uart_sam0_tx_halt()
179 return -EINVAL; in uart_sam0_tx_halt()
197 if (!dev_data->async_cb) { in uart_sam0_notify_rx_processed()
201 if (dev_data->rx_processed_len == processed) { in uart_sam0_notify_rx_processed()
208 .buf = dev_data->rx_buf, in uart_sam0_notify_rx_processed()
209 .offset = dev_data->rx_processed_len, in uart_sam0_notify_rx_processed()
210 .len = processed - dev_data->rx_processed_len, in uart_sam0_notify_rx_processed()
214 dev_data->rx_processed_len = processed; in uart_sam0_notify_rx_processed()
216 dev_data->async_cb(dev_data->dev, in uart_sam0_notify_rx_processed()
217 &evt, dev_data->async_cb_data); in uart_sam0_notify_rx_processed()
229 const struct device *dev = dev_data->dev; in uart_sam0_dma_rx_done()
230 const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg; in uart_sam0_dma_rx_done()
231 SercomUsart * const regs = cfg->regs; in uart_sam0_dma_rx_done()
234 if (dev_data->rx_len == 0U) { in uart_sam0_dma_rx_done()
239 uart_sam0_notify_rx_processed(dev_data, dev_data->rx_len); in uart_sam0_dma_rx_done()
241 if (dev_data->async_cb) { in uart_sam0_dma_rx_done()
245 .buf = dev_data->rx_buf, in uart_sam0_dma_rx_done()
249 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_dma_rx_done()
253 if (!dev_data->rx_next_len) { in uart_sam0_dma_rx_done()
254 dev_data->rx_buf = NULL; in uart_sam0_dma_rx_done()
255 dev_data->rx_len = 0U; in uart_sam0_dma_rx_done()
257 if (dev_data->async_cb) { in uart_sam0_dma_rx_done()
262 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_dma_rx_done()
269 dev_data->rx_buf = dev_data->rx_next_buf; in uart_sam0_dma_rx_done()
270 dev_data->rx_len = dev_data->rx_next_len; in uart_sam0_dma_rx_done()
271 dev_data->rx_next_buf = NULL; in uart_sam0_dma_rx_done()
272 dev_data->rx_next_len = 0U; in uart_sam0_dma_rx_done()
273 dev_data->rx_processed_len = 0U; in uart_sam0_dma_rx_done()
275 dma_reload(cfg->dma_dev, cfg->rx_dma_channel, in uart_sam0_dma_rx_done()
276 (uint32_t)(&(regs->DATA.reg)), in uart_sam0_dma_rx_done()
277 (uint32_t)dev_data->rx_buf, dev_data->rx_len); in uart_sam0_dma_rx_done()
285 if (dev_data->rx_timeout_time != SYS_FOREVER_US) { in uart_sam0_dma_rx_done()
286 dev_data->rx_waiting_for_irq = true; in uart_sam0_dma_rx_done()
287 regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC; in uart_sam0_dma_rx_done()
293 dma_start(cfg->dma_dev, cfg->rx_dma_channel); in uart_sam0_dma_rx_done()
299 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_dma_rx_done()
309 const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg; in uart_sam0_rx_timeout()
310 SercomUsart * const regs = cfg->regs; in uart_sam0_rx_timeout()
314 if (dev_data->rx_len == 0U) { in uart_sam0_rx_timeout()
324 * it handle things instead when we re-enable IRQs. in uart_sam0_rx_timeout()
326 dma_stop(cfg->dma_dev, cfg->rx_dma_channel); in uart_sam0_rx_timeout()
327 if (dma_get_status(cfg->dma_dev, cfg->rx_dma_channel, in uart_sam0_rx_timeout()
333 uint8_t *rx_dma_start = dev_data->rx_buf + dev_data->rx_len - in uart_sam0_rx_timeout()
335 size_t rx_processed = rx_dma_start - dev_data->rx_buf; in uart_sam0_rx_timeout()
341 dma_reload(cfg->dma_dev, cfg->rx_dma_channel, in uart_sam0_rx_timeout()
342 (uint32_t)(&(regs->DATA.reg)), in uart_sam0_rx_timeout()
344 dev_data->rx_len - rx_processed); in uart_sam0_rx_timeout()
346 dev_data->rx_waiting_for_irq = true; in uart_sam0_rx_timeout()
347 regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC; in uart_sam0_rx_timeout()
356 if (dev_data->rx_timeout_from_isr) { in uart_sam0_rx_timeout()
357 dev_data->rx_timeout_from_isr = false; in uart_sam0_rx_timeout()
358 k_work_reschedule(&dev_data->rx_timeout_work, in uart_sam0_rx_timeout()
359 K_USEC(dev_data->rx_timeout_chunk)); in uart_sam0_rx_timeout()
365 uint32_t elapsed = now - dev_data->rx_timeout_start; in uart_sam0_rx_timeout()
367 if (elapsed >= dev_data->rx_timeout_time) { in uart_sam0_rx_timeout()
377 uint32_t remaining = MIN(dev_data->rx_timeout_time - elapsed, in uart_sam0_rx_timeout()
378 dev_data->rx_timeout_chunk); in uart_sam0_rx_timeout()
380 k_work_reschedule(&dev_data->rx_timeout_work, in uart_sam0_rx_timeout()
395 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_configure()
396 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_configure()
397 SercomUsart * const usart = cfg->regs; in uart_sam0_configure()
401 usart->CTRLA.bit.ENABLE = 0; in uart_sam0_configure()
404 if (new_cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) { in uart_sam0_configure()
408 return -ENOTSUP; in uart_sam0_configure()
411 dev_data->config_cache.flow_ctrl = new_cfg->flow_ctrl; in uart_sam0_configure()
413 SERCOM_USART_CTRLA_Type CTRLA_temp = usart->CTRLA; in uart_sam0_configure()
414 SERCOM_USART_CTRLB_Type CTRLB_temp = usart->CTRLB; in uart_sam0_configure()
416 switch (new_cfg->parity) { in uart_sam0_configure()
429 return -ENOTSUP; in uart_sam0_configure()
432 dev_data->config_cache.parity = new_cfg->parity; in uart_sam0_configure()
434 switch (new_cfg->stop_bits) { in uart_sam0_configure()
442 return -ENOTSUP; in uart_sam0_configure()
445 dev_data->config_cache.stop_bits = new_cfg->stop_bits; in uart_sam0_configure()
447 switch (new_cfg->data_bits) { in uart_sam0_configure()
464 return -ENOTSUP; in uart_sam0_configure()
467 dev_data->config_cache.data_bits = new_cfg->data_bits; in uart_sam0_configure()
470 CTRLB_temp.bit.COLDEN = cfg->pads; in uart_sam0_configure()
473 usart->CTRLA = CTRLA_temp; in uart_sam0_configure()
476 usart->CTRLB = CTRLB_temp; in uart_sam0_configure()
479 retval = uart_sam0_set_baudrate(usart, new_cfg->baudrate, in uart_sam0_configure()
485 dev_data->config_cache.baudrate = new_cfg->baudrate; in uart_sam0_configure()
487 usart->CTRLA.bit.ENABLE = 1; in uart_sam0_configure()
496 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_config_get()
498 memcpy(out_cfg, &(dev_data->config_cache), in uart_sam0_config_get()
499 sizeof(dev_data->config_cache)); in uart_sam0_config_get()
508 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_init()
509 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_init()
511 SercomUsart * const usart = cfg->regs; in uart_sam0_init()
515 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 | in uart_sam0_init()
519 *cfg->mclk |= cfg->mclk_mask; in uart_sam0_init()
522 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in uart_sam0_init()
526 PM->APBCMASK.reg |= cfg->pm_apbcmask; in uart_sam0_init()
530 usart->INTENCLR.reg = SERCOM_USART_INTENCLR_MASK; in uart_sam0_init()
534 usart->CTRLA.reg = in uart_sam0_init()
535 cfg->pads in uart_sam0_init()
547 retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in uart_sam0_init()
552 dev_data->config_cache.flow_ctrl = UART_CFG_FLOW_CTRL_NONE; in uart_sam0_init()
553 dev_data->config_cache.parity = UART_CFG_PARITY_NONE; in uart_sam0_init()
554 dev_data->config_cache.stop_bits = UART_CFG_STOP_BITS_1; in uart_sam0_init()
555 dev_data->config_cache.data_bits = UART_CFG_DATA_BITS_8; in uart_sam0_init()
558 usart->CTRLB.reg = SERCOM_USART_CTRLB_CHSIZE(0) | in uart_sam0_init()
562 retval = uart_sam0_set_baudrate(usart, cfg->baudrate, in uart_sam0_init()
567 dev_data->config_cache.baudrate = cfg->baudrate; in uart_sam0_init()
570 cfg->irq_config_func(dev); in uart_sam0_init()
574 dev_data->dev = dev; in uart_sam0_init()
575 dev_data->cfg = cfg; in uart_sam0_init()
576 if (!device_is_ready(cfg->dma_dev)) { in uart_sam0_init()
577 return -ENODEV; in uart_sam0_init()
580 k_work_init_delayable(&dev_data->tx_timeout_work, uart_sam0_tx_timeout); in uart_sam0_init()
581 k_work_init_delayable(&dev_data->rx_timeout_work, uart_sam0_rx_timeout); in uart_sam0_init()
583 if (cfg->tx_dma_channel != 0xFFU) { in uart_sam0_init()
594 dma_cfg.dma_slot = cfg->tx_dma_request; in uart_sam0_init()
597 dma_blk.dest_address = (uint32_t)(&(usart->DATA.reg)); in uart_sam0_init()
600 retval = dma_config(cfg->dma_dev, cfg->tx_dma_channel, in uart_sam0_init()
607 if (cfg->rx_dma_channel != 0xFFU) { in uart_sam0_init()
618 dma_cfg.dma_slot = cfg->rx_dma_request; in uart_sam0_init()
621 dma_blk.source_address = (uint32_t)(&(usart->DATA.reg)); in uart_sam0_init()
624 retval = dma_config(cfg->dma_dev, cfg->rx_dma_channel, in uart_sam0_init()
633 usart->CTRLA.bit.ENABLE = 1; in uart_sam0_init()
641 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_poll_in()
643 SercomUsart * const usart = config->regs; in uart_sam0_poll_in()
645 if (!usart->INTFLAG.bit.RXC) { in uart_sam0_poll_in()
646 return -EBUSY; in uart_sam0_poll_in()
649 *c = (unsigned char)usart->DATA.reg; in uart_sam0_poll_in()
655 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_poll_out()
657 SercomUsart * const usart = config->regs; in uart_sam0_poll_out()
659 while (!usart->INTFLAG.bit.DRE) { in uart_sam0_poll_out()
663 usart->DATA.reg = c; in uart_sam0_poll_out()
668 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_err_check()
670 SercomUsart * const regs = config->regs; in uart_sam0_err_check()
673 if (regs->STATUS.reg & SERCOM_USART_STATUS_BUFOVF) { in uart_sam0_err_check()
677 if (regs->STATUS.reg & SERCOM_USART_STATUS_FERR) { in uart_sam0_err_check()
681 if (regs->STATUS.reg & SERCOM_USART_STATUS_PERR) { in uart_sam0_err_check()
686 if (regs->STATUS.reg & SERCOM_USART_STATUS_ISF) { in uart_sam0_err_check()
690 if (regs->STATUS.reg & SERCOM_USART_STATUS_COLL) { in uart_sam0_err_check()
694 regs->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF in uart_sam0_err_check()
700 regs->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF in uart_sam0_err_check()
713 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_isr()
716 if (dev_data->cb) { in uart_sam0_isr()
717 dev_data->cb(dev, dev_data->cb_data); in uart_sam0_isr()
722 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_isr()
723 SercomUsart * const regs = cfg->regs; in uart_sam0_isr()
725 if (dev_data->tx_len && regs->INTFLAG.bit.TXC) { in uart_sam0_isr()
726 regs->INTENCLR.reg = SERCOM_USART_INTENCLR_TXC; in uart_sam0_isr()
728 k_work_cancel_delayable(&dev_data->tx_timeout_work); in uart_sam0_isr()
735 .buf = dev_data->tx_buf, in uart_sam0_isr()
736 .len = dev_data->tx_len, in uart_sam0_isr()
740 dev_data->tx_buf = NULL; in uart_sam0_isr()
741 dev_data->tx_len = 0U; in uart_sam0_isr()
743 if (evt.data.tx.len != 0U && dev_data->async_cb) { in uart_sam0_isr()
744 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_isr()
750 if (dev_data->rx_len && regs->INTFLAG.bit.RXC && in uart_sam0_isr()
751 dev_data->rx_waiting_for_irq) { in uart_sam0_isr()
752 dev_data->rx_waiting_for_irq = false; in uart_sam0_isr()
753 regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC; in uart_sam0_isr()
756 if (dev_data->rx_next_len == 0U && dev_data->async_cb) { in uart_sam0_isr()
761 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_isr()
768 if (dev_data->rx_timeout_time != SYS_FOREVER_US) { in uart_sam0_isr()
769 dev_data->rx_timeout_from_isr = true; in uart_sam0_isr()
770 dev_data->rx_timeout_start = k_uptime_get_32(); in uart_sam0_isr()
771 k_work_reschedule(&dev_data->rx_timeout_work, in uart_sam0_isr()
772 K_USEC(dev_data->rx_timeout_chunk)); in uart_sam0_isr()
776 dma_start(cfg->dma_dev, cfg->rx_dma_channel); in uart_sam0_isr()
788 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_fifo_fill()
789 SercomUsart *regs = config->regs; in uart_sam0_fifo_fill()
791 if (regs->INTFLAG.bit.DRE && len >= 1) { in uart_sam0_fifo_fill()
792 regs->DATA.reg = tx_data[0]; in uart_sam0_fifo_fill()
801 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_tx_enable()
802 SercomUsart * const regs = config->regs; in uart_sam0_irq_tx_enable()
804 regs->INTENSET.reg = SERCOM_USART_INTENSET_DRE in uart_sam0_irq_tx_enable()
810 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_tx_disable()
811 SercomUsart * const regs = config->regs; in uart_sam0_irq_tx_disable()
813 regs->INTENCLR.reg = SERCOM_USART_INTENCLR_DRE in uart_sam0_irq_tx_disable()
819 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_tx_ready()
820 SercomUsart * const regs = config->regs; in uart_sam0_irq_tx_ready()
822 return (regs->INTFLAG.bit.DRE != 0) && (regs->INTENSET.bit.DRE != 0); in uart_sam0_irq_tx_ready()
827 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_tx_complete()
828 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_irq_tx_complete()
829 SercomUsart * const regs = config->regs; in uart_sam0_irq_tx_complete()
831 return (dev_data->txc_cache != 0) && (regs->INTENSET.bit.TXC != 0); in uart_sam0_irq_tx_complete()
836 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_rx_enable()
837 SercomUsart * const regs = config->regs; in uart_sam0_irq_rx_enable()
839 regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC; in uart_sam0_irq_rx_enable()
844 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_rx_disable()
845 SercomUsart * const regs = config->regs; in uart_sam0_irq_rx_disable()
847 regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC; in uart_sam0_irq_rx_disable()
852 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_rx_ready()
853 SercomUsart * const regs = config->regs; in uart_sam0_irq_rx_ready()
855 return regs->INTFLAG.bit.RXC != 0; in uart_sam0_irq_rx_ready()
861 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_fifo_read()
862 SercomUsart * const regs = config->regs; in uart_sam0_fifo_read()
864 if (regs->INTFLAG.bit.RXC) { in uart_sam0_fifo_read()
865 uint8_t ch = regs->DATA.reg; in uart_sam0_fifo_read()
871 return -EINVAL; in uart_sam0_fifo_read()
879 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_is_pending()
880 SercomUsart * const regs = config->regs; in uart_sam0_irq_is_pending()
882 return (regs->INTENSET.reg & regs->INTFLAG.reg) != 0; in uart_sam0_irq_is_pending()
888 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_err_enable()
889 SercomUsart * const regs = config->regs; in uart_sam0_irq_err_enable()
891 regs->INTENSET.reg |= SERCOM_USART_INTENCLR_ERROR; in uart_sam0_irq_err_enable()
897 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_err_disable()
898 SercomUsart * const regs = config->regs; in uart_sam0_irq_err_disable()
900 regs->INTENCLR.reg |= SERCOM_USART_INTENSET_ERROR; in uart_sam0_irq_err_disable()
908 const struct uart_sam0_dev_cfg *config = dev->config; in uart_sam0_irq_update()
909 SercomUsart * const regs = config->regs; in uart_sam0_irq_update()
917 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_irq_update()
919 dev_data->txc_cache = regs->INTFLAG.bit.TXC; in uart_sam0_irq_update()
920 regs->INTFLAG.reg = SERCOM_USART_INTENCLR_ERROR in uart_sam0_irq_update()
924 | (dev_data->txc_cache << SERCOM_USART_INTENCLR_TXC_Pos); in uart_sam0_irq_update()
926 regs->INTFLAG.reg = SERCOM_USART_INTENCLR_RXS; in uart_sam0_irq_update()
935 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_irq_callback_set()
937 dev_data->cb = cb; in uart_sam0_irq_callback_set()
938 dev_data->cb_data = cb_data; in uart_sam0_irq_callback_set()
941 dev_data->async_cb = NULL; in uart_sam0_irq_callback_set()
942 dev_data->async_cb_data = NULL; in uart_sam0_irq_callback_set()
953 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_callback_set()
955 dev_data->async_cb = callback; in uart_sam0_callback_set()
956 dev_data->async_cb_data = user_data; in uart_sam0_callback_set()
959 dev_data->cb = NULL; in uart_sam0_callback_set()
960 dev_data->cb_data = NULL; in uart_sam0_callback_set()
970 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_tx()
971 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_tx()
972 SercomUsart *regs = cfg->regs; in uart_sam0_tx()
975 if (cfg->tx_dma_channel == 0xFFU) { in uart_sam0_tx()
976 return -ENOTSUP; in uart_sam0_tx()
980 return -EINVAL; in uart_sam0_tx()
985 if (dev_data->tx_len != 0U) { in uart_sam0_tx()
986 retval = -EBUSY; in uart_sam0_tx()
990 dev_data->tx_buf = buf; in uart_sam0_tx()
991 dev_data->tx_len = len; in uart_sam0_tx()
995 retval = dma_reload(cfg->dma_dev, cfg->tx_dma_channel, (uint32_t)buf, in uart_sam0_tx()
996 (uint32_t)(&(regs->DATA.reg)), len); in uart_sam0_tx()
1002 k_work_reschedule(&dev_data->tx_timeout_work, in uart_sam0_tx()
1006 return dma_start(cfg->dma_dev, cfg->tx_dma_channel); in uart_sam0_tx()
1014 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_tx_abort()
1015 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_tx_abort()
1017 if (cfg->tx_dma_channel == 0xFFU) { in uart_sam0_tx_abort()
1018 return -ENOTSUP; in uart_sam0_tx_abort()
1021 k_work_cancel_delayable(&dev_data->tx_timeout_work); in uart_sam0_tx_abort()
1030 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_rx_enable()
1031 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_rx_enable()
1032 SercomUsart *regs = cfg->regs; in uart_sam0_rx_enable()
1035 if (cfg->rx_dma_channel == 0xFFU) { in uart_sam0_rx_enable()
1036 return -ENOTSUP; in uart_sam0_rx_enable()
1040 return -EINVAL; in uart_sam0_rx_enable()
1045 if (dev_data->rx_len != 0U) { in uart_sam0_rx_enable()
1046 retval = -EBUSY; in uart_sam0_rx_enable()
1051 while (regs->INTFLAG.bit.RXC) { in uart_sam0_rx_enable()
1052 char discard = regs->DATA.reg; in uart_sam0_rx_enable()
1057 retval = dma_reload(cfg->dma_dev, cfg->rx_dma_channel, in uart_sam0_rx_enable()
1058 (uint32_t)(&(regs->DATA.reg)), in uart_sam0_rx_enable()
1064 dev_data->rx_buf = buf; in uart_sam0_rx_enable()
1065 dev_data->rx_len = len; in uart_sam0_rx_enable()
1066 dev_data->rx_processed_len = 0U; in uart_sam0_rx_enable()
1067 dev_data->rx_waiting_for_irq = true; in uart_sam0_rx_enable()
1068 dev_data->rx_timeout_from_isr = true; in uart_sam0_rx_enable()
1069 dev_data->rx_timeout_time = timeout; in uart_sam0_rx_enable()
1070 dev_data->rx_timeout_chunk = MAX(timeout / 4U, 1); in uart_sam0_rx_enable()
1072 regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC; in uart_sam0_rx_enable()
1086 return -EINVAL; in uart_sam0_rx_buf_rsp()
1089 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_rx_buf_rsp()
1093 if (dev_data->rx_len == 0U) { in uart_sam0_rx_buf_rsp()
1094 retval = -EACCES; in uart_sam0_rx_buf_rsp()
1098 if (dev_data->rx_next_len != 0U) { in uart_sam0_rx_buf_rsp()
1099 retval = -EBUSY; in uart_sam0_rx_buf_rsp()
1103 dev_data->rx_next_buf = buf; in uart_sam0_rx_buf_rsp()
1104 dev_data->rx_next_len = len; in uart_sam0_rx_buf_rsp()
1116 struct uart_sam0_dev_data *const dev_data = dev->data; in uart_sam0_rx_disable()
1117 const struct uart_sam0_dev_cfg *const cfg = dev->config; in uart_sam0_rx_disable()
1118 SercomUsart * const regs = cfg->regs; in uart_sam0_rx_disable()
1121 k_work_cancel_delayable(&dev_data->rx_timeout_work); in uart_sam0_rx_disable()
1125 if (dev_data->rx_len == 0U) { in uart_sam0_rx_disable()
1127 return -EINVAL; in uart_sam0_rx_disable()
1130 regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC; in uart_sam0_rx_disable()
1131 dma_stop(cfg->dma_dev, cfg->rx_dma_channel); in uart_sam0_rx_disable()
1134 if (dma_get_status(cfg->dma_dev, cfg->rx_dma_channel, in uart_sam0_rx_disable()
1136 size_t rx_processed = dev_data->rx_len - st.pending_length; in uart_sam0_rx_disable()
1144 .buf = dev_data->rx_buf, in uart_sam0_rx_disable()
1148 dev_data->rx_buf = NULL; in uart_sam0_rx_disable()
1149 dev_data->rx_len = 0U; in uart_sam0_rx_disable()
1151 if (dev_data->async_cb) { in uart_sam0_rx_disable()
1152 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_rx_disable()
1155 if (dev_data->rx_next_len) { in uart_sam0_rx_disable()
1159 .buf = dev_data->rx_next_buf, in uart_sam0_rx_disable()
1163 dev_data->rx_next_buf = NULL; in uart_sam0_rx_disable()
1164 dev_data->rx_next_len = 0U; in uart_sam0_rx_disable()
1166 if (dev_data->async_cb) { in uart_sam0_rx_disable()
1167 dev_data->async_cb(dev, &next_evt, dev_data->async_cb_data); in uart_sam0_rx_disable()
1172 if (dev_data->async_cb) { in uart_sam0_rx_disable()
1173 dev_data->async_cb(dev, &evt, dev_data->async_cb_data); in uart_sam0_rx_disable()