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/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
13 compatible = "mmio-sram";
17 flash-controller@407e0000 {
19 #address-cells = <1>;
20 #size-cells = <1>;
23 compatible = "soc-nv-flash";
29 compatible = "renesas,ra-sce7-rng";
34 channel-count = <11>;
[all …]
Dr7fa6m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa6e2bx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
[all …]
Dr7fa6m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
21 port = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
[all …]
Dr7fa6e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
23 port = <6>;
24 gpio-controller;
25 #gpio-cells = <2>;
[all …]
Dr7fa6m5xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
21 port = <6>;
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
[all …]
Dr7fa6m4ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &sci2;
12 /delete-node/ &sci3;
13 /delete-node/ &ioport6;
14 /delete-node/ &ioport7;
15 /delete-node/ &ioport8;
20 compatible = "mmio-sram";
25 compatible = "renesas,ra-spi";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4w1ad2cng.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
20 flash-controller@407e0000 {
22 compatible = "soc-nv-flash";
28 compatible = "renesas,ra-sci";
30 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa4e2b93cfm.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 /delete-node/ &iic0;
[all …]
Dr7fa4m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
23 port = <6>;
24 gpio-controller;
25 #gpio-cells = <2>;
[all …]
Dr7fa4m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
13 /delete-node/ &adc1;
18 compatible = "mmio-sram";
23 compatible = "renesas,ra-gpio-ioport";
25 port = <6>;
26 gpio-controller;
[all …]
/Zephyr-latest/dts/bindings/gpio/
Drenesas,rz-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 gpio-consumer{
8 out-gpio = <&gpio8 2 (GPIO_PULL_UP);
14 Example above will configure pin 2 port 8:
15 - Using interrupt TINT10
16 - Set Pullup
19 compatible: "renesas,rz-gpio"
22 - name: base.yaml
23 property-allowlist:
24 - status
[all …]
Drenesas,ra-gpio-ioport.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA GPIO IO port
6 compatible: "renesas,ra-gpio-ioport"
8 include: [gpio-controller.yaml, base.yaml]
14 port:
20 description: Array of vbatt pin on port
22 port-irqs:
23 type: phandle-array
24 description: Port irq which this port can be use
26 port-irq-names:
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_rzt2m.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/gpio/renesas-rzt2m-gpio.h>
32 /* config defines in include/zephyr/dt-bindings/gpio/renesas-rzt2m-gpio.h */
59 uint8_t port; member
90 /* Port m output data store */
93 const struct rzt2m_gpio_config *config = dev->config; in rzt2m_gpio_get_p_reg()
95 return (volatile uint8_t *)(config->port_nsr + config->port); in rzt2m_gpio_get_p_reg()
98 /* Port m input data store */
101 const struct rzt2m_gpio_config *config = dev->config; in rzt2m_gpio_get_pin_reg()
103 return (volatile uint8_t *)(config->port_nsr + PINm_OFFSET + config->port); in rzt2m_gpio_get_pin_reg()
[all …]
Dgpio_renesas_rz.c4 * SPDX-License-Identifier: Apache-2.0
20 #define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__)
21 #define LOG_DEV_DBG(dev, format, ...) LOG_DBG("%s:" #format, (dev)->name, ##__VA_ARGS__)
60 const struct gpio_rz_config *config = dev->config; in gpio_rz_pin_get_config()
61 bsp_io_port_pin_t port_pin = config->fsp_port | pin; in gpio_rz_pin_get_config()
71 bsp_io_port_t port = (port_pin >> 8U) & 0xFF; in gpio_rz_pin_config_get_raw() local
80 adr_offset = (uint8_t)GPIO_RZ_REG_OFFSET(port, pin); in gpio_rz_pin_config_get_raw()
100 const struct gpio_rz_config *config = dev->config; in gpio_rz_pin_configure()
101 struct gpio_rz_data *data = dev->data; in gpio_rz_pin_configure()
102 bsp_io_port_pin_t port_pin = config->fsp_port | pin; in gpio_rz_pin_configure()
[all …]
Dgpio_mcux_rgpio.c2 * Copyright 2023-2024, NXP
4 * SPDX-License-Identifier: Apache-2.0
21 ((const struct mcux_rgpio_config *)(_dev)->config)
22 #define DEV_DATA(_dev) ((struct mcux_rgpio_data *)(_dev)->data)
40 /* port ISR callback routine address */
48 const struct mcux_rgpio_config *config = dev->config; in mcux_rgpio_configure()
54 if ((config->common.port_pin_mask & BIT(pin)) == 0) { in mcux_rgpio_configure()
55 return -ENOTSUP; in mcux_rgpio_configure()
58 /* Some SOCs have non-contiguous gpio pin layouts, account for this */ in mcux_rgpio_configure()
60 if ((config->common.port_pin_mask & BIT(i)) == 0) { in mcux_rgpio_configure()
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_nxp_imx_netc.c4 * SPDX-License-Identifier: Apache-2.0
28 struct netc_eth_data *data = dev->data; in netc_eth_rx()
38 result = EP_GetRxFrameSize(&data->handle, 0, &length); in netc_eth_rx()
40 ret = -ENOBUFS; in netc_eth_rx()
46 ret = -EIO; in netc_eth_rx()
51 result = EP_ReceiveFrameCopy(&data->handle, 0, data->rx_frame, length, NULL); in netc_eth_rx()
54 ret = -EIO; in netc_eth_rx()
59 pkt = net_pkt_rx_alloc_with_buffer(data->iface, length, AF_UNSPEC, 0, NETC_TIMEOUT); in netc_eth_rx()
61 eth_stats_update_errors_rx(data->iface); in netc_eth_rx()
62 ret = -ENOBUFS; in netc_eth_rx()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-1.6.rst7 release introduces the unified Kernel replacing the separate nano- and
8 micro-kernels and simplifying the overall Zephyr architecture and programming
10 Support for the ARM Cortex-M0/M0+ family was added and board support for
11 Cortex-M was expanded.
22 * Added support for several ARM Cortex-M boards
32 * Removed deprecated Tasks IRQs.
34 * Added DLIST to operate in all elements of a doubly-linked list.
52 * ARM: Added support for ARM Cortex-M0/M0+.
55 * x86: Changed IRQ controller to return -1 if cannot determine source vector.
77 * SPI: Fixed typos in SPI port numbers.
[all …]
/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi.c2 * Copyright 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
27 read-while-write hazards. This configuration is not recommended."
41 /* Structure tracking LUT offset and usage per each port */
47 /* flexspi device data should be stored in RAM to avoid read-while-write hazards */
75 struct memc_flexspi_data *data = dev->data; in memc_flexspi_wait_bus_idle()
77 while (false == FLEXSPI_GetBusIdleStatus(data->base)) { in memc_flexspi_wait_bus_idle()
83 struct memc_flexspi_data *data = dev->data; in memc_flexspi_is_running_xip()
85 return data->xip; in memc_flexspi_is_running_xip()
90 flexspi_port_t port, uint32_t freq_hz) in memc_flexspi_update_clock() argument
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
21 /* This driver configures the ERU for a target port/pin combination for rising/falling */
24 /* unset on a negative edge (or vice-versa depending on the configuration). The value of */
28 /* The ERU configurations for supported port/pin combinations are stored in a devicetree file */
29 /* dts/arm/infineon/xmc4xxx_x_x-intc.dtsi. The configurations are stored in the opaque array */
31 /* dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h. */
60 struct intc_xmc4xxx_data *data = dev->data; in intc_xmc4xxx_gpio_enable_interrupt()
61 const struct intc_xmc4xxx_config *config = dev->config; in intc_xmc4xxx_gpio_enable_interrupt()
62 int ret = -ENOTSUP; in intc_xmc4xxx_gpio_enable_interrupt()
[all …]
Dintc_dw.c4 * SPDX-License-Identifier: Apache-2.0
9 /* This implementation supports only the regular irqs
31 intr_bitpos = find_lsb_set(intr_status) - 1; in dw_ictl_dispatch_child_isrs()
41 const struct dw_ictl_config *config = dev->config; in dw_ictl_initialize()
43 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_initialize()
46 regs->irq_inten_l = 0U; in dw_ictl_initialize()
47 regs->irq_inten_h = 0U; in dw_ictl_initialize()
54 const struct dw_ictl_config *config = dev->config; in dw_ictl_isr()
56 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_isr()
58 dw_ictl_dispatch_child_isrs(regs->irq_finalstatus_l, in dw_ictl_isr()
[all …]

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