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/Zephyr-latest/dts/bindings/clock/
Dst,stm32f4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F4 Main PLL node binding:
11 Up to 2 output clocks could be supported and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19 The PLL output frequency must not exceed 80 MHz.
22 compatible: "st,stm32f4-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
[all …]
Dst,stm32g0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PLL node binding for STM32G0 devices
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 64 MHz.
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32f4-plli2s-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F4 PLL I2S node binding:
7 Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
9 1 output clocks supported, the frequency can be computed with the following formula:
11 f(PLL_R) = f(VCO clock) / PLLR --> PLLI2S
13 with f(VCO clock) = f(PLL clock input) × (PLLNI2S / PLLM)
16 compatible: "st,stm32f4-plli2s-clock"
18 include: [clock-controller.yaml, base.yaml]
21 "#clock-cells":
24 mul-n:
[all …]
Dst,stm32f2-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F2 Main PLL node binding:
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
17 The PLL output frequency must not exceed 168 MHz.
20 compatible: "st,stm32f2-pll-clock"
22 include: [clock-controller.yaml, base.yaml]
25 "#clock-cells":
[all …]
Dst,stm32wb-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB and STM32WL PLL node.
7 It can be used to describe 2 different PLLs: PLL, PLLSAI1.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed:
[all …]
Dst,stm32f7-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F7 Main PLL node binding:
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
26 clocks:
[all …]
Dst,stm32u0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32U0 Main PLL node binding:
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 122 MHz.
22 compatible: "st,stm32u0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32l4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PLL node binding for STM32L4 and STM32L5 devices
7 It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed 80 MHz.
[all …]
Dst,stm32f411-plli2s-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F411 PLL I2S node binding:
7 Fully configurable I2S dedicated PLL.
9 1 output clocks supported, the frequency can be computed with the following formula:
11 f(PLLI2S_R) = f(VCO clock) / PLLI2S R --> PLLI2S
13 with f(VCO clock) = f(PLL I2S clock input) × (PLLI2S N / PLLI2S M)
16 compatible: "st,stm32f411-plli2s-clock"
18 include: st,stm32f4-plli2s-clock.yaml
21 div-m:
25 Division factor for the PLL input clock
[all …]
Dst,stm32h7-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PLL node binding for STM32H7 devices
7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
18 f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
19 f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
23 The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32h7-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df0_i2c1_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
29 &pll {
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
[all …]
Df3_i2c1_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
29 &pll {
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
[all …]
Dg4_i2c1_hsi_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
21 &pll {
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
[all …]
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
21 &pll {
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
[all …]
Dg0_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
21 &pll {
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
[all …]
Dl4_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
26 &pll {
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
[all …]
Dl4_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
26 &pll {
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
[all …]
Df4_i2s2_pll.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
29 &pll {
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f100Xb.dtsi6 * SPDX-License-Identifier: Apache-2.0
17 clocks {
18 /delete-node/ pll;
20 pll: pll { label
21 #clock-cells = <0>;
22 compatible = "st,stm32f100-pll-clock";
28 compatible = "st,stm32f100", "st,stm32f1", "simple-bus";
30 flash-controller@40022000 {
33 erase-block-size = <DT_SIZE_K(1)>;
38 compatible = "st,stm32-spi";
[all …]
/Zephyr-latest/boards/makerbase/mks_canable_v20/
Dmks_canable_v20.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
8 #include <st/g4/stm32g431c(6-8-b)tx-pinctrl.dtsi>
12 compatible = "makerbase,mks-canable-v20";
26 compatible = "gpio-leds";
29 label = "blue-status D2";
33 label = "green-word D3";
39 /* Internal 16 MHz clock used to drive PLL */
48 /* Adjust the pll for a SYSTEM Clock of 160 MHz */
49 &pll {
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Df2_f4_f7_pll_100_hsi_16_ahb_2.overlay4 * SPDX-License-Identifier: Apache-2.0
16 &pll {
17 div-m = <8>;
18 mul-n = <200>;
19 div-p = <4>;
20 clocks = <&clk_hsi>;
25 clocks = <&pll>;
26 ahb-prescaler = <2>;
27 clock-frequency = <DT_FREQ_M(50)>; /* Pll Output (100) / AHB prescaler */
28 apb1-prescaler = <2>;
[all …]
Df1_pll_64_hsi_8.overlay4 * SPDX-License-Identifier: Apache-2.0
16 &pll {
18 clocks = <&clk_hsi>;
23 clocks = <&pll>;
24 clock-frequency = <DT_FREQ_M(64)>;
Dpll_32_hsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
16 &pll {
19 clocks = <&clk_hsi>;
24 clocks = <&pll>;
25 clock-frequency = <DT_FREQ_M(32)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * Warning: This overlay clears clocks back to a state equivalent to what could
13 /* Clocks clean up config
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * Warning: This overlay clears clocks back to a state equivalent to what could
13 /* Clocks clean up config
19 /delete-property/ hse-bypass;
20 /delete-property/ clock-frequency;
25 /delete-property/ hsi-div;
40 &pll {
41 /delete-property/ div-m;
42 /delete-property/ mul-n;
43 /delete-property/ div-p;
[all …]

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