1# Copyright (c) 2023, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32F411 PLL I2S node binding:
6
7  Fully configurable I2S dedicated PLL.
8
9  1 output clocks supported, the frequency can be computed with the following formula:
10
11    f(PLLI2S_R) = f(VCO clock) / PLLI2S R  --> PLLI2S
12
13      with f(VCO clock) = f(PLL I2S clock input) × (PLLI2S N / PLLI2S M)
14
15
16compatible: "st,stm32f411-plli2s-clock"
17
18include: st,stm32f4-plli2s-clock.yaml
19
20properties:
21  div-m:
22    type: int
23    required: true
24    description: |
25        Division factor for the PLL input clock
26        Valid range: 2 - 63
27
28  div-q:
29    type: int
30    description: |
31        PLLI2S division factor for I2S Clocks to supply USB/SDIO/RNG
32    enum:
33      - 2
34      - 3
35      - 4
36      - 5
37      - 6
38      - 7
39      - 8
40      - 9
41      - 10
42      - 11
43      - 12
44      - 13
45      - 14
46      - 15
47