Lines Matching +full:pll +full:- +full:clocks

2 # SPDX-License-Identifier: Apache-2.0
5   PLL node binding for STM32G0 devices
11   PLL can have up to 3 output clocks and for each output clock, the
14     f(PLL_P) = f(VCO clock) / PLLP  --> to I2S
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
16     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
18       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20   The PLL output frequency must not exceed 64 MHz.
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
30   clocks:
33   div-m:
37         Division factor for PLL input clock
38         Valid range: 1 - 8
40   mul-n:
44         Main PLL multiplication factor for VCO
45         Valid range: 8 - 86
47   div-p:
50         PLL division factor for PLL P output
51         Valid range: 2 - 32
53   div-q:
56         PLL division factor for PLL Q output
57         Valid range: 2 - 8
59   div-r:
63         PLL division factor for PLLCLK (system clock)
64         Valid range: 2 - 8