Lines Matching +full:pll +full:- +full:clocks

2 # SPDX-License-Identifier: Apache-2.0
5   STM32U0 Main PLL node binding:
11   PLL can have up to 3 output clocks and for each output clock, the
14     f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
16     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
18       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20   The PLL output frequency must not exceed 122 MHz.
22 compatible: "st,stm32u0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
30   clocks:
33   div-m:
37         Division factor M of the PLL
39         Valid range: 1 - 8
41   mul-n:
45         PLL frequency multiplication factor N
46         Valid range: 4 - 127
48   div-p:
51         PLL VCO division factor P
52         Valid range: 2 - 32
54   div-q:
57         PLL VCO division factor Q
58         Valid range: 2 - 8
60   div-r:
64         PLL VCO division factor R
65         Valid range: 2 - 8