Lines Matching +full:pll +full:- +full:clocks

2 # SPDX-License-Identifier: Apache-2.0
5   STM32F7 Main PLL node binding:
9   Up to 2 output clocks could be supported and for each output clock, the
12     f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
13     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
15       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23   "#clock-cells":
26   clocks:
29   div-m:
33         Division factor for the PLL input clock
34         Valid range: 2 - 63
36   mul-n:
40         PLL multiplication factor for VCO
41         Valid range: 50 - 432
43   div-p:
47         PLL division factor for PLLCLK
49       - 2
50       - 4
51       - 6
52       - 8
54   div-q:
57         PLL division factor for PLL48CK
58         Valid range: 2 - 15