Lines Matching +full:pll +full:- +full:clocks

2 # SPDX-License-Identifier: Apache-2.0
5   STM32F4 Main PLL node binding:
11   Up to 2 output clocks could be supported and for each output clock, the
14     f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
17       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19   The PLL output frequency must not exceed 80 MHz.
22 compatible: "st,stm32f4-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
30   clocks:
33   div-m:
37         Division factor for the PLL input clock
38         Valid range: 2 - 63
40   mul-n:
44         Main PLL multiplication factor for VCO
45         Valid range: 50 - 432
47   div-p:
51         Main PLL division factor for PLLSAI2CLK
53       - 2
54       - 4
55       - 6
56       - 8
58   div-q:
61         Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
62         generator clocks.
63         Valid range: 2 - 15
65   div-r:
68         Main PLL (PLL) division factor for I2S and DFSDM
69         generator clocks.
70         Valid range: 2 - 7