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Searched +full:mram +full:- +full:cfg (Results 1 – 25 of 25) sorted by relevance

/Zephyr-latest/drivers/can/
Dcan_sam0.c7 * SPDX-License-Identifier: Apache-2.0
24 mem_addr_t mram; member
35 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_read_reg()
36 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_read_reg()
38 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam0_read_reg()
43 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_write_reg()
44 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_write_reg()
60 return can_mcan_sys_write_reg(sam_config->base, reg, val); in can_sam0_write_reg()
65 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_read_mram()
66 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_read_mram()
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/Zephyr-latest/dts/arm/atmel/
Dsame5x.dtsi5 * SPDX-License-Identifier: Apache-2.0
13 compatible = "atmel,sam0-gmac";
16 interrupt-names = "gmac";
19 num-queues = <1>;
20 local-mac-address = [00 00 00 00 00 00];
24 compatible = "atmel,sam-mdio";
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "atmel,sam0-can";
36 interrupt-names = "int0", "int1";
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Dsamc21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 adc-1 = &adc1;
13 sercom-4 = &sercom4;
14 sercom-5 = &sercom5;
19 compatible = "atmel,sam0-adc";
22 interrupt-names = "resrdy";
24 clock-names = "GCLK", "MCLK";
27 #io-channel-cells = <1>;
34 compatible = "atmel,sam0-sercom";
38 clock-names = "GCLK", "MCLK";
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Dsame70.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
21 zephyr,flash-controller = &eefc;
29 #address-cells = <1>;
30 #size-cells = <0>;
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/Zephyr-latest/dts/bindings/can/
Dbosch,m_can-base.yaml3 include: [can-fd-controller.yaml]
6 bosch,mram-cfg:
12 <offset std-filter-elements ext-filter-elements rx-fifo0-elements rx-fifo1-elements
13 rx-buffer-elements tx-event-fifo-elements tx-buffer-elements>
16 from. This is normally set to 0x0 when using a non-shared message RAM. The remaining cells
20 11-bit Filter 0-128 elements / 0-128 words
21 29-bit Filter 0-64 elements / 0-128 words
22 Rx FIFO 0 0-64 elements / 0-1152 words
23 Rx FIFO 1 0-64 elements / 0-1152 words
24 Rx Buffers 0-64 elements / 0-1152 words
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Dti,tcan4x5x.yaml2 # SPDX-License-Identifier: Apache-2.0
12 spi-max-frequency = <18000000>;
13 clock-frequency = <40000000>;
14 device-state-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
15 device-wake-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
16 reset-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
17 int-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
21 can-transceiver {
22 max-bitrate = <8000000>;
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/Zephyr-latest/boards/shields/tcan4550evm/
Dtcan4550evm.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
17 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
22 /* reduced spi-max-frequency to accommodate flywire connections */
23 spi-max-frequency = <2000000>;
25 clock-frequency = <40000000>;
26 device-state-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */
27 device-wake-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
28 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */
29 int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */
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/Zephyr-latest/dts/arm/st/g0/
Dstm32g0b1.dtsi3 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
5 * SPDX-License-Identifier: Apache-2.0
13 clk_hsi48: clk-hsi48 {
14 #clock-cells = <0>;
15 compatible = "st,stm32-hsi48-clock";
16 clock-frequency = <DT_FREQ_M(48)>;
22 compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";
25 pinctrl: pin-controller@50000000 {
27 compatible = "st,stm32-gpio";
28 gpio-controller;
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/Zephyr-latest/dts/arm/st/g4/
Dstm32g491.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-fdcan";
16 reg-names = "m_can", "message_ram";
18 interrupt-names = "int0", "int1";
20 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
25 compatible = "st,stm32-timers";
30 interrupt-names = "brk", "up", "trgcom", "cc";
35 compatible = "st,stm32-pwm";
37 #pwm-cells = <3>;
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Dstm32g473.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g473", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
24 compatible = "st,stm32-pwm";
26 #pwm-cells = <3>;
31 compatible = "st,stm32-adc";
36 #io-channel-cells = <1>;
41 sampling-times = <3 7 13 25 48 93 248 641>;
42 st,adc-sequencer = "FULLY_CONFIGURABLE";
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Dstm32g4.dtsi6 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32g4_clock.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/numaker-m46x-pinctrl.h>
10 #include <zephyr/dt-bindings/clock/numaker_m46x_clock.h>
11 #include <zephyr/dt-bindings/reset/numaker_m46x_reset.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &fmc;
26 #address-cells = <1>;
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Dm2l31x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
10 #include <zephyr/dt-bindings/clock/numaker_m2l31x_clock.h>
11 #include <zephyr/dt-bindings/reset/numaker_m2l31x_reset.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &rmc;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/Zephyr-latest/dts/arm/st/h7/
Dstm32h723.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/display/panel.h>
11 #include <zephyr/dt-bindings/flash_controller/ospi.h>
15 compatible = "st,stm32h723", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <32>;
21 erase-block-size = <DT_SIZE_K(128)>;
23 max-erase-time = <4000>;
28 compatible = "st,stm32-uart";
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Dstm32h7.dtsi7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
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/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S0x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m33f";
21 #address-cells = <1>;
22 #size-cells = <1>;
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Dnxp_lpc55S1x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33f";
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Dnxp_lpc55S3x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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/Zephyr-latest/dts/common/nordic/
Dnrf9280.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
10 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
11 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
12 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
13 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
15 /delete-node/ &sw_pwm;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 #address-cells = <1>;
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Dnrf54h20.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
11 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
12 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
13 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
14 #include <zephyr/dt-bindings/misc/nordic-tddconf.h>
15 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
16 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
18 /delete-node/ &sw_pwm;
21 #address-cells = <1>;
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/Zephyr-latest/include/zephyr/drivers/can/
Dcan_mcan.h5 * SPDX-License-Identifier: Apache-2.0
399 * @name Indexes for the cells in the devicetree bosch,mram-cfg property
402 * These match the description of the cells in the bosch,m_can-base devicetree binding.
408 /** std-filter-elements cell index */
410 /** ext-filter-elements cell index */
412 /** rx-fifo0-elements cell index */
414 /** rx-fifo1-elements cell index */
416 /** rx-buffer-elements cell index */
418 /** tx-event-fifo-elements cell index */
420 /** tx-buffer-elements cell index */
[all …]
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
10 #include <zephyr/dt-bindings/flash_controller/xspi.h>
17 #clock-cells = <0>;
18 compatible = "st,stm32u5-pll-clock";
24 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
26 pinctrl: pin-controller@42020000 {
28 compatible = "st,stm32-gpio";
29 gpio-controller;
30 #gpio-cells = <2>;
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Dstm32h5.dtsi2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/reset/stm32h5_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
[all …]
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5.dtsi7 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/adc/adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/clock/stm32u5_clock.h>
15 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #include <zephyr/dt-bindings/flash_controller/ospi.h>
18 #include <zephyr/dt-bindings/reset/stm32u5_reset.h>
19 #include <zephyr/dt-bindings/dma/stm32_dma.h>
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-4.0.rst15 is now the standard way to provide device-specific protection to data at rest. (:github:`76222`)
18 :ref:`ZMS <zms_api>` is a new key-value storage subsystem compatible with all non-volatile storage
19 types, including traditional NOR flash and advanced technologies like RRAM and MRAM that support
25 runtime configuration through vendor specific APIs. Initially the :dtcompatible:`nordic,nrf-comp`,
26 :dtcompatible:`nordic,nrf-lpcomp` and :dtcompatible:`nxp,kinetis-acmp` are supported.
31 Initially implemented drivers include a simple :dtcompatible:`zephyr,gpio-steppers` and a complex
32 sensor-less stall-detection capable with integrated ramp-controller :dtcompatible:`adi,tmc5041`.
50 directory for :zephyr:code-sample-category:`code samples <samples>`.
70 * :cve:`2024-8798`: Under embargo until 2024-11-22
71 * :cve:`2024-10395`: Under embargo until 2025-01-23
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