1/* 2 * Copyright (c) 2022 metraTec 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <mem.h> 11#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 compatible = "arm,cortex-m33f"; 20 reg = <0>; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 mpu: mpu@e000ed90 { 25 compatible = "arm,armv8m-mpu"; 26 reg = <0xe000ed90 0x40>; 27 }; 28 }; 29 }; 30}; 31 32&sram { 33 #address-cells = <1>; 34 #size-cells = <1>; 35 36 /* lpc55_0x Memory configurations: 37 * 38 * LPC5502: RAMX: 16K, SRAM0: 32K 39 * LPC55x04: RAMX: 16K, SRAM0: 32K, SRAM1: 16K 40 * LPC55x06: RAMX: 16K, SRAM0: 32K, SRAM1: 16K, SRAM2: 16K, SRAM3: 16k 41 */ 42 sramx: memory@4000000 { 43 compatible = "mmio-sram"; 44 reg = <0x04000000 DT_SIZE_K(16)>; 45 }; 46 sram0: memory@20000000 { 47 compatible = "mmio-sram"; 48 reg = <0x20000000 DT_SIZE_K(32)>; 49 }; 50 sram1: memory@20008000 { 51 compatible = "mmio-sram"; 52 reg = <0x20008000 DT_SIZE_K(16)>; 53 }; 54 sram2: memory@2000C000 { 55 compatible = "mmio-sram"; 56 reg = <0x2000C000 DT_SIZE_K(16)>; 57 }; 58 sram3: memory@20010000 { 59 compatible = "mmio-sram"; 60 reg = <0x20010000 DT_SIZE_K(16)>; 61 }; 62}; 63 64&peripheral { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 68 syscon: syscon@0 { 69 compatible = "nxp,lpc-syscon"; 70 reg = <0x0 0x4000>; 71 #clock-cells = <1>; 72 reset: reset { 73 compatible = "nxp,lpc-syscon-reset"; 74 #reset-cells = <1>; 75 }; 76 }; 77 78 iap: flash-controller@34000 { 79 compatible = "nxp,iap-fmc55"; 80 reg = <0x34000 0x18>; 81 status = "disabled"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 85 flash0: flash@0 { 86 compatible = "soc-nv-flash"; 87 reg = <0x0 DT_SIZE_K(246)>; 88 erase-block-size = <512>; 89 write-block-size = <512>; 90 }; 91 92 flash_reserved: flash@3d800 { 93 compatible = "soc-nv-flash"; 94 reg = <0x0003d800 DT_SIZE_K(10)>; 95 status = "disabled"; 96 }; 97 98 uuid: flash@3fc70 { 99 compatible = "nxp,lpc-uid"; 100 reg = <0x3fc70 0x10>; 101 }; 102 103 boot_rom: flash@3000000 { 104 compatible = "soc-nv-flash"; 105 reg = <0x3000000 DT_SIZE_K(128)>; 106 }; 107 }; 108 109 iocon: iocon@1000 { 110 compatible = "nxp,lpc-iocon"; 111 reg = <0x1000 0x100>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0x0 0x1000 0x100>; 115 pinctrl: pinctrl { 116 compatible = "nxp,lpc-iocon-pinctrl"; 117 }; 118 }; 119 120 gpio: gpio@8c000 { 121 compatible = "nxp,lpc-gpio"; 122 reg = <0x8c000 0x2488>; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 gpio0: gpio@0 { 126 compatible = "nxp,lpc-gpio-port"; 127 int-source = "pint"; 128 gpio-controller; 129 #gpio-cells = <2>; 130 reg = <0>; 131 }; 132 133 gpio1: gpio@1 { 134 compatible = "nxp,lpc-gpio-port"; 135 int-source = "pint"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 reg = <1>; 139 }; 140 }; 141 142 pint: pint@4000 { 143 compatible = "nxp,pint"; 144 reg = <0x4000 0x1000>; 145 interrupt-controller; 146 #interrupt-cells = <1>; 147 #address-cells = <0>; 148 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 149 <32 2>, <33 2>, <34 2>, <35 2>; 150 num-lines = <8>; 151 num-inputs = <64>; 152 }; 153 154 flexcomm0: flexcomm@86000 { 155 compatible = "nxp,lpc-flexcomm"; 156 reg = <0x86000 0x1000>; 157 interrupts = <14 0>; 158 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 159 resets = <&reset NXP_SYSCON_RESET(1, 11)>; 160 status = "disabled"; 161 }; 162 163 flexcomm1: flexcomm@87000 { 164 compatible = "nxp,lpc-flexcomm"; 165 reg = <0x87000 0x1000>; 166 interrupts = <15 0>; 167 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 168 resets = <&reset NXP_SYSCON_RESET(1, 12)>; 169 status = "disabled"; 170 }; 171 172 flexcomm2: flexcomm@88000 { 173 compatible = "nxp,lpc-flexcomm"; 174 reg = <0x88000 0x1000>; 175 interrupts = <16 0>; 176 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 177 resets = <&reset NXP_SYSCON_RESET(1, 13)>; 178 status = "disabled"; 179 }; 180 181 flexcomm3: flexcomm@89000 { 182 compatible = "nxp,lpc-flexcomm"; 183 reg = <0x89000 0x1000>; 184 interrupts = <17 0>; 185 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 186 resets = <&reset NXP_SYSCON_RESET(1, 14)>; 187 status = "disabled"; 188 }; 189 190 flexcomm4: flexcomm@8a000 { 191 compatible = "nxp,lpc-flexcomm"; 192 reg = <0x8a000 0x1000>; 193 interrupts = <18 0>; 194 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 195 resets = <&reset NXP_SYSCON_RESET(1, 15)>; 196 status = "disabled"; 197 }; 198 199 flexcomm5: flexcomm@96000 { 200 compatible = "nxp,lpc-flexcomm"; 201 reg = <0x96000 0x1000>; 202 interrupts = <19 0>; 203 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 204 resets = <&reset NXP_SYSCON_RESET(1, 16)>; 205 status = "disabled"; 206 }; 207 208 flexcomm6: flexcomm@97000 { 209 compatible = "nxp,lpc-flexcomm"; 210 reg = <0x97000 0x1000>; 211 interrupts = <20 0>; 212 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 213 resets = <&reset NXP_SYSCON_RESET(1, 17)>; 214 status = "disabled"; 215 }; 216 217 flexcomm7: flexcomm@98000 { 218 compatible = "nxp,lpc-flexcomm"; 219 reg = <0x98000 0x1000>; 220 interrupts = <21 0>; 221 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 222 resets = <&reset NXP_SYSCON_RESET(1, 18)>; 223 status = "disabled"; 224 }; 225 226 hs_lspi: spi@9f000 { 227 compatible = "nxp,lpc-spi"; 228 reg = <0x9f000 0x1000>; 229 interrupts = <59 0>; 230 clocks = <&syscon MCUX_HS_SPI_CLK>; 231 resets = <&reset NXP_SYSCON_RESET(2, 28)>; 232 status = "disabled"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 }; 236 237 can0: can@9d000 { 238 compatible = "nxp,lpc-mcan"; 239 reg = <0x9d000 0x1000>; 240 interrupts = <43 0>, <44 0>; 241 interrupt-names = "int0", "int1"; 242 clocks = <&syscon MCUX_MCAN_CLK>; 243 resets = <&reset NXP_SYSCON_RESET(1, 7)>; 244 bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>; 245 status = "disabled"; 246 }; 247 248 rng: rng@3a000 { 249 compatible = "nxp,lpc-rng"; 250 reg = <0x3a000 0x1000>; 251 status = "okay"; 252 }; 253}; 254 255&nvic { 256 arm,num-irq-priority-bits = <3>; 257}; 258
