1/*
2 * Copyright (c) 2021 Guðni Már Gilbert
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/g4/stm32g4.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
12
13		fdcan2: can@40006800 {
14			compatible = "st,stm32-fdcan";
15			reg = <0x40006800 0x400>, <0x4000a400 0x6a0>;
16			reg-names = "m_can", "message_ram";
17			interrupts = <86 0>, <87 0>;
18			interrupt-names = "int0", "int1";
19			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
20			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
21			status = "disabled";
22		};
23
24		timers20: timers@40015000 {
25			compatible = "st,stm32-timers";
26			reg = <0x40015000 0x400>;
27			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
28			resets = <&rctl STM32_RESET(APB2, 20U)>;
29			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
30			interrupt-names = "brk", "up", "trgcom", "cc";
31			st,prescaler = <0>;
32			status = "disabled";
33
34			pwm {
35				compatible = "st,stm32-pwm";
36				status = "disabled";
37				#pwm-cells = <3>;
38			};
39		};
40
41		dma1: dma@40020000 {
42			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
43			dma-requests = <8>;
44		};
45
46		dma2: dma@40020400 {
47			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
48			dma-requests = <8>;
49			dma-offset = <8>;
50		};
51
52		dmamux1: dmamux@40020800 {
53			dma-channels = <16>;
54		};
55
56		adc3: adc@50000400 {
57			compatible = "st,stm32-adc";
58			reg = <0x50000400 0x100>;
59			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
60			interrupts = <47 0>;
61			status = "disabled";
62			#io-channel-cells = <1>;
63			resolutions = <STM32_ADC_RES(12, 0x00)
64				       STM32_ADC_RES(10, 0x01)
65				       STM32_ADC_RES(8, 0x02)
66				       STM32_ADC_RES(6, 0x03)>;
67			sampling-times = <3 7 13 25 48 93 248 641>;
68			st,adc-sequencer = "FULLY_CONFIGURABLE";
69			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
70		};
71
72		uart5: serial@40005000 {
73			compatible = "st,stm32-uart";
74			reg = <0x40005000 0x400>;
75			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
76			resets = <&rctl STM32_RESET(APB1L, 20U)>;
77			interrupts = <53 0>;
78			status = "disabled";
79		};
80	};
81};
82