1/*
2 * Copyright (c) 2021 Guðni Már Gilbert
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/g4/stm32g491.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32g473", "st,stm32g4", "simple-bus";
12
13		timers5: timers@40000c00 {
14			compatible = "st,stm32-timers";
15			reg = <0x40000c00 0x400>;
16			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
17			resets = <&rctl STM32_RESET(APB1L, 3U)>;
18			interrupts = <50 0>;
19			interrupt-names = "global";
20			st,prescaler = <0>;
21			status = "disabled";
22
23			pwm {
24				compatible = "st,stm32-pwm";
25				status = "disabled";
26				#pwm-cells = <3>;
27			};
28		};
29
30		adc4: adc@50000500 {
31			compatible = "st,stm32-adc";
32			reg = <0x50000500 0x100>;
33			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
34			interrupts = <61 0>;
35			status = "disabled";
36			#io-channel-cells = <1>;
37			resolutions = <STM32_ADC_RES(12, 0x00)
38				       STM32_ADC_RES(10, 0x01)
39				       STM32_ADC_RES(8, 0x02)
40				       STM32_ADC_RES(6, 0x03)>;
41			sampling-times = <3 7 13 25 48 93 248 641>;
42			st,adc-sequencer = "FULLY_CONFIGURABLE";
43			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
44		};
45
46		adc5: adc@50000600 {
47			compatible = "st,stm32-adc";
48			reg = <0x50000600 0x100>;
49			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
50			interrupts = <62 0>;
51			status = "disabled";
52			#io-channel-cells = <1>;
53			resolutions = <STM32_ADC_RES(12, 0x00)
54				       STM32_ADC_RES(10, 0x01)
55				       STM32_ADC_RES(8, 0x02)
56				       STM32_ADC_RES(6, 0x03)>;
57			sampling-times = <3 7 13 25 48 93 248 641>;
58			st,adc-sequencer = "FULLY_CONFIGURABLE";
59			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
60		};
61
62		spi4: spi@40013c00 {
63			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
64			#address-cells = <1>;
65			#size-cells = <0>;
66			reg = <0x40013c00 0x400>;
67			clocks = <&rcc STM32_CLOCK(APB2, 15U)>;
68			interrupts = <84 5>;
69			status = "disabled";
70		};
71
72		dac2: dac@50000c00 {
73			compatible = "st,stm32-dac";
74			reg = <0x50000c00 0x400>;
75			clocks = <&rcc STM32_CLOCK(AHB2, 17U)>;
76			status = "disabled";
77			#io-channel-cells = <1>;
78		};
79
80		dac4: dac@50001400 {
81			compatible = "st,stm32-dac";
82			reg = <0x50001400 0x400>;
83			clocks = <&rcc STM32_CLOCK(AHB2, 19U)>;
84			status = "disabled";
85			#io-channel-cells = <1>;
86		};
87
88		i2c4: i2c@40008400 {
89			compatible = "st,stm32-i2c-v2";
90			clock-frequency = <I2C_BITRATE_STANDARD>;
91			#address-cells = <1>;
92			#size-cells = <0>;
93			reg = <0x40008400 0x400>;
94			clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
95			interrupts = <82 0>, <83 0>;
96			interrupt-names = "event", "error";
97			status = "disabled";
98		};
99
100		fdcan3: can@40006c00 {
101			compatible = "st,stm32-fdcan";
102			reg = <0x40006c00 0x400>, <0x4000a400 0x9f0>;
103			reg-names = "m_can", "message_ram";
104			interrupts = <88 0>, <89 0>;
105			interrupt-names = "int0", "int1";
106			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
107			bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>;
108			status = "disabled";
109		};
110	};
111
112	smbus4: smbus4 {
113		compatible = "st,stm32-smbus";
114		#address-cells = <1>;
115		#size-cells = <0>;
116		i2c = <&i2c4>;
117		status = "disabled";
118	};
119};
120