1/* 2 * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 12#include <mem.h> 13#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 14 15/ { 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "arm,cortex-m33f"; 22 reg = <0>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv8m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 }; 32}; 33 34&sram { 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 sramx: memory@4000000 { 39 compatible = "zephyr,memory-region", "mmio-sram"; 40 reg = <0x4000000 DT_SIZE_K(16)>; 41 zephyr,memory-region = "SRAMX"; 42 }; 43 44 sram0: memory@20000000 { 45 compatible = "zephyr,memory-region", "mmio-sram"; 46 reg = <0x20000000 DT_SIZE_K(32)>; 47 zephyr,memory-region = "SRAM0"; 48 }; 49 50 sram1: memory@20008000 { 51 compatible = "zephyr,memory-region", "mmio-sram"; 52 reg = <0x20008000 DT_SIZE_K(16)>; 53 zephyr,memory-region = "SRAM1"; 54 }; 55 56 sram2: memory@2000c000 { 57 compatible = "zephyr,memory-region", "mmio-sram"; 58 reg = <0x2000c000 DT_SIZE_K(16)>; 59 zephyr,memory-region = "SRAM2"; 60 }; 61 62 usb_sram: memory@20010000 { 63 /* Connected to USB bus*/ 64 compatible = "zephyr,memory-region", "mmio-sram"; 65 reg = <0x20010000 DT_SIZE_K(16)>; 66 zephyr,memory-region = "USB_SRAM"; 67 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; 68 }; 69}; 70 71&peripheral { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 75 syscon: syscon@0 { 76 compatible = "nxp,lpc-syscon"; 77 reg = <0x0 0x4000>; 78 #clock-cells = <1>; 79 reset: reset { 80 compatible = "nxp,lpc-syscon-reset"; 81 #reset-cells = <1>; 82 }; 83 }; 84 85 iap: flash-controller@34000 { 86 compatible = "nxp,iap-fmc55"; 87 reg = <0x34000 0x18>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 status = "disabled"; 91 92 flash0: flash@0 { 93 compatible = "soc-nv-flash"; 94 reg = <0x0 DT_SIZE_K(246)>; 95 erase-block-size = <512>; 96 write-block-size = <512>; 97 }; 98 99 flash_reserved: flash@3d800 { 100 compatible = "soc-nv-flash"; 101 reg = <0x0003d800 DT_SIZE_K(10)>; 102 status = "disabled"; 103 }; 104 105 uuid: flash@3fc70 { 106 compatible = "nxp,lpc-uid"; 107 reg = <0x3fc70 0x10>; 108 }; 109 110 boot_rom: flash@3000000 { 111 compatible = "soc-nv-flash"; 112 reg = <0x3000000 DT_SIZE_K(128)>; 113 }; 114 }; 115 116 iocon: iocon@1000 { 117 compatible = "nxp,lpc-iocon"; 118 reg = <0x1000 0x100>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0x0 0x1000 0x100>; 122 pinctrl: pinctrl { 123 compatible = "nxp,lpc-iocon-pinctrl"; 124 }; 125 }; 126 127 gpio: gpio@8c000 { 128 compatible = "nxp,lpc-gpio"; 129 reg = <0x8c000 0x2488>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 gpio0: gpio@0 { 134 compatible = "nxp,lpc-gpio-port"; 135 reg = <0>; 136 int-source = "pint"; 137 gpio-controller; 138 #gpio-cells = <2>; 139 }; 140 141 gpio1: gpio@1 { 142 compatible = "nxp,lpc-gpio-port"; 143 reg = <1>; 144 int-source = "pint"; 145 gpio-controller; 146 #gpio-cells = <2>; 147 }; 148 }; 149 150 pint: pint@4000 { 151 compatible = "nxp,pint"; 152 reg = <0x4000 0x1000>; 153 interrupt-controller; 154 #interrupt-cells = <1>; 155 #address-cells = <0>; 156 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 157 <32 2>, <33 2>, <34 2>, <35 2>; 158 num-lines = <8>; 159 num-inputs = <64>; 160 }; 161 162 ctimer0: ctimer@8000 { 163 compatible = "nxp,lpc-ctimer"; 164 reg = <0x8000 0x1000>; 165 interrupts = <10 0>; 166 status = "disabled"; 167 clk-source = <3>; 168 clocks = <&syscon MCUX_CTIMER0_CLK>; 169 mode = <0>; 170 input = <0>; 171 prescale = <0>; 172 }; 173 174 ctimer1: ctimer@9000 { 175 compatible = "nxp,lpc-ctimer"; 176 reg = <0x9000 0x1000>; 177 interrupts = <11 0>; 178 status = "disabled"; 179 clk-source = <3>; 180 clocks = <&syscon MCUX_CTIMER1_CLK>; 181 mode = <0>; 182 input = <0>; 183 prescale = <0>; 184 }; 185 186 ctimer2: ctimer@28000 { 187 compatible = "nxp,lpc-ctimer"; 188 reg = <0x28000 0x1000>; 189 interrupts = <36 0>; 190 status = "disabled"; 191 clk-source = <3>; 192 clocks = <&syscon MCUX_CTIMER2_CLK>; 193 mode = <0>; 194 input = <0>; 195 prescale = <0>; 196 }; 197 198 ctimer3: ctimer@29000 { 199 compatible = "nxp,lpc-ctimer"; 200 reg = <0x29000 0x1000>; 201 interrupts = <13 0>; 202 status = "disabled"; 203 clk-source = <3>; 204 clocks = <&syscon MCUX_CTIMER3_CLK>; 205 mode = <0>; 206 input = <0>; 207 prescale = <0>; 208 }; 209 210 ctimer4: ctimer@2A000 { 211 compatible = "nxp,lpc-ctimer"; 212 reg = <0x2A000 0x1000>; 213 interrupts = <37 0>; 214 status = "disabled"; 215 clk-source = <3>; 216 clocks = <&syscon MCUX_CTIMER4_CLK>; 217 mode = <0>; 218 input = <0>; 219 prescale = <0>; 220 }; 221 222 flexcomm0: flexcomm@86000 { 223 compatible = "nxp,lpc-flexcomm"; 224 reg = <0x86000 0x1000>; 225 interrupts = <14 0>; 226 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 227 resets = <&reset NXP_SYSCON_RESET(1, 11)>; 228 status = "disabled"; 229 }; 230 231 flexcomm1: flexcomm@87000 { 232 compatible = "nxp,lpc-flexcomm"; 233 reg = <0x87000 0x1000>; 234 interrupts = <15 0>; 235 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 236 resets = <&reset NXP_SYSCON_RESET(1, 12)>; 237 status = "disabled"; 238 }; 239 240 flexcomm2: flexcomm@88000 { 241 compatible = "nxp,lpc-flexcomm"; 242 reg = <0x88000 0x1000>; 243 interrupts = <16 0>; 244 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 245 resets = <&reset NXP_SYSCON_RESET(1, 13)>; 246 status = "disabled"; 247 }; 248 249 flexcomm3: flexcomm@89000 { 250 compatible = "nxp,lpc-flexcomm"; 251 reg = <0x89000 0x1000>; 252 interrupts = <17 0>; 253 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 254 resets = <&reset NXP_SYSCON_RESET(1, 14)>; 255 status = "disabled"; 256 }; 257 258 flexcomm4: flexcomm@8a000 { 259 compatible = "nxp,lpc-flexcomm"; 260 reg = <0x8a000 0x1000>; 261 interrupts = <18 0>; 262 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 263 resets = <&reset NXP_SYSCON_RESET(1, 15)>; 264 status = "disabled"; 265 }; 266 267 flexcomm5: flexcomm@96000 { 268 compatible = "nxp,lpc-flexcomm"; 269 reg = <0x96000 0x1000>; 270 interrupts = <19 0>; 271 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 272 resets = <&reset NXP_SYSCON_RESET(1, 16)>; 273 status = "disabled"; 274 }; 275 276 flexcomm6: flexcomm@97000 { 277 compatible = "nxp,lpc-flexcomm"; 278 reg = <0x97000 0x1000>; 279 interrupts = <20 0>; 280 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 281 resets = <&reset NXP_SYSCON_RESET(1, 17)>; 282 status = "disabled"; 283 }; 284 285 flexcomm7: flexcomm@98000 { 286 compatible = "nxp,lpc-flexcomm"; 287 reg = <0x98000 0x1000>; 288 interrupts = <21 0>; 289 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 290 resets = <&reset NXP_SYSCON_RESET(1, 18)>; 291 status = "disabled"; 292 }; 293 294 can0: can@9d000 { 295 compatible = "nxp,lpc-mcan"; 296 reg = <0x9d000 0x1000>; 297 interrupts = <43 0>, <44 0>; 298 interrupt-names = "int0", "int1"; 299 clocks = <&syscon MCUX_MCAN_CLK>; 300 resets = <&reset NXP_SYSCON_RESET(1, 7)>; 301 bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>; 302 status = "disabled"; 303 }; 304 305 hs_lspi: spi@9f000 { 306 compatible = "nxp,lpc-spi"; 307 reg = <0x9f000 0x1000>; 308 interrupts = <59 0>; 309 clocks = <&syscon MCUX_HS_SPI_CLK>; 310 resets = <&reset NXP_SYSCON_RESET(2, 28)>; 311 status = "disabled"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 316 rng: rng@3a000 { 317 compatible = "nxp,lpc-rng"; 318 reg = <0x3a000 0x1000>; 319 status = "okay"; 320 }; 321 322 usbhs: usbhs@94000 { 323 compatible = "nxp,lpcip3511"; 324 reg = <0x94000 0x1000>; 325 interrupts = <47 1>; 326 num-bidir-endpoints = <6>; 327 status = "disabled"; 328 }; 329 330 usbphy1: usbphy@38000 { 331 compatible = "nxp,usbphy"; 332 reg = <0x38000 0x1000>; 333 status = "disabled"; 334 }; 335}; 336 337&nvic { 338 arm,num-irq-priority-bits = <3>; 339}; 340
