Searched full:pllr (Results 1 – 19 of 19) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f4-plli2s-clock.yaml | 11 f(PLL_R) = f(VCO clock) / PLLR --> PLLI2S
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| D | st,stm32g4-pll-clock.yaml | 16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32g0-pll-clock.yaml | 16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32u0-pll-clock.yaml | 16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32wba-pll-clock.yaml | 18 f(PLL_R) = f(VCO clock) / PLLR
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| D | st,stm32wb-pll-clock.yaml | 19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
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| D | st,stm32l4-pll-clock.yaml | 19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32u5-pll-clock.yaml | 18 f(PLL_R) = f(VCO clock) / PLLR
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32g4.c | 68 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
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| D | clock_stm32g0_u0.c | 64 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
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| D | clock_stm32_ll_common.h | 28 #define pllr(v) z_pllr(v) macro
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| D | clock_stm32l4_l5_wb_wl.c | 83 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
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| D | clock_stm32f2_f4_f7.c | 100 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
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| /Zephyr-latest/boards/renesas/mck_ra8t1/ |
| D | mck_ra8t1.dts | 74 pllr {
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| /Zephyr-latest/dts/arm/renesas/ra/ra8/ |
| D | r7fa8m1xh.dtsi | 72 pllr: pllr { label
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| D | r7fa8t1xh.dtsi | 70 pllr: pllr { label
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| D | r7fa8d1xh.dtsi | 102 pllr: pllr { label
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| /Zephyr-latest/boards/renesas/ek_ra8d1/ |
| D | ek_ra8d1.dts | 109 pllr {
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| /Zephyr-latest/boards/renesas/ek_ra8m1/ |
| D | ek_ra8m1.dts | 146 pllr {
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