Searched full:pllm (Results 1 – 21 of 21) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f4-plli2s-clock.yaml | 7 Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
13 with f(VCO clock) = f(PLL clock input) × (PLLNI2S / PLLM)
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| D | st,stm32g4-pll-clock.yaml | 8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32f4-pll-clock.yaml | 8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32g0-pll-clock.yaml | 8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32u0-pll-clock.yaml | 8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32wba-pll-clock.yaml | 10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32wb-pll-clock.yaml | 11 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32l4-pll-clock.yaml | 11 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32u5-pll-clock.yaml | 10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32f7-pll-clock.yaml | 15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32f2-pll-clock.yaml | 15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32h7rs-pll-clock.yaml | 10 an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
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| D | st,stm32h7-pll-clock.yaml | 11 an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_agilex5_ll.c | 26 /* Read pllglob and pllm registers */ in get_ref_clk()
83 clock_val = get_ref_clk(CLKCTRL_MAINPLL(PLLGLOB), CLKCTRL_MAINPLL(PLLM)); in get_clk_freq()
90 clock_val = get_ref_clk(CLKCTRL_PERPLL(PLLGLOB), CLKCTRL_PERPLL(PLLM)); in get_clk_freq()
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| D | clock_stm32f2_f4_f7.c | 103 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
110 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32g4.c | 66 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32g0_u0.c | 62 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32_ll_common.h | 19 #define pllm(v) z_pllm(v) macro
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| D | clock_stm32l4_l5_wb_wl.c | 81 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32_ll_h7.c | 994 uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; local
1014 * PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
1018 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
1027 if (pllm != 0U) {
1030 pllvco = ((float_t)HSE_VALUE / (float_t)pllm) *
1036 pllvco = ((float_t)CSI_VALUE / (float_t)pllm) *
1045 pllvco = ((float_t)hsivalue / (float_t)pllm) *
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| D | clock_stm32_ll_u5.c | 455 * (MSI/PLLM or HSE/PLLM when HSE is > 16MHz in set_epod_booster()
459 * Divide PLL1 input freq (MSI/PLL or HSE/PLLM) in set_epod_booster()
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