1 /*
2 *
3 * Copyright (c) 2021 Linaro Limited
4 * Copyright (c) 2022 Thomas Stranger
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9
10 #include <soc.h>
11 #include <stm32_ll_bus.h>
12 #include <stm32_ll_pwr.h>
13 #include <stm32_ll_rcc.h>
14 #include <stm32_ll_utils.h>
15 #include <stm32_ll_system.h>
16 #include <zephyr/arch/cpu.h>
17 #include <zephyr/drivers/clock_control.h>
18 #include <zephyr/sys/util.h>
19 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
20
21
22 /* Macros to fill up prescaler values */
23 #define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
24 #define ahb_prescaler(v) z_ahb_prescaler(v)
25
26 #define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
27 #define apb1_prescaler(v) z_apb1_prescaler(v)
28
29 #define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
30 #define apb2_prescaler(v) z_apb2_prescaler(v)
31
32 #define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
33 #define apb3_prescaler(v) z_apb3_prescaler(v)
34
35 #define PLL1_ID 1
36 #define PLL2_ID 2
37 #define PLL3_ID 3
38
get_bus_clock(uint32_t clock,uint32_t prescaler)39 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
40 {
41 return clock / prescaler;
42 }
43
get_msis_frequency(void)44 static uint32_t get_msis_frequency(void)
45 {
46 return __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
47 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
48 LL_RCC_MSIS_GetRange() :
49 LL_RCC_MSIS_GetRangeAfterStandby()));
50 }
51
52 __unused
53 /** @brief returns the pll source frequency of given pll_id */
get_pllsrc_frequency(size_t pll_id)54 static uint32_t get_pllsrc_frequency(size_t pll_id)
55 {
56
57 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) ||
58 (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) ||
59 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) {
60 return STM32_HSI_FREQ;
61 } else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) ||
62 (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) ||
63 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) {
64 return STM32_HSE_FREQ;
65 } else if ((IS_ENABLED(STM32_PLL_SRC_MSIS) && pll_id == PLL1_ID) ||
66 (IS_ENABLED(STM32_PLL2_SRC_MSIS) && pll_id == PLL2_ID) ||
67 (IS_ENABLED(STM32_PLL3_SRC_MSIS) && pll_id == PLL3_ID)) {
68 return get_msis_frequency();
69 }
70
71 __ASSERT(0, "No PLL Source configured");
72 return 0;
73 }
74
get_startup_frequency(void)75 static uint32_t get_startup_frequency(void)
76 {
77 switch (LL_RCC_GetSysClkSource()) {
78 case LL_RCC_SYS_CLKSOURCE_STATUS_MSIS:
79 return get_msis_frequency();
80 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
81 return STM32_HSI_FREQ;
82 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
83 return STM32_HSE_FREQ;
84 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
85 return get_pllsrc_frequency(PLL1_ID);
86 default:
87 __ASSERT(0, "Unexpected startup freq");
88 return 0;
89 }
90 }
91
92 __unused
get_pllout_frequency(uint32_t pllsrc_freq,int pllm_div,int plln_mul,int pllout_div)93 static uint32_t get_pllout_frequency(uint32_t pllsrc_freq,
94 int pllm_div,
95 int plln_mul,
96 int pllout_div)
97 {
98 __ASSERT_NO_MSG(pllm_div && pllout_div);
99
100 return (pllsrc_freq / pllm_div) * plln_mul / pllout_div;
101 }
102
get_sysclk_frequency(void)103 static uint32_t get_sysclk_frequency(void)
104 {
105 #if defined(STM32_SYSCLK_SRC_PLL)
106 return get_pllout_frequency(get_pllsrc_frequency(PLL1_ID),
107 STM32_PLL_M_DIVISOR,
108 STM32_PLL_N_MULTIPLIER,
109 STM32_PLL_R_DIVISOR);
110 #elif defined(STM32_SYSCLK_SRC_MSIS)
111 return get_msis_frequency();
112 #elif defined(STM32_SYSCLK_SRC_HSE)
113 return STM32_HSE_FREQ;
114 #elif defined(STM32_SYSCLK_SRC_HSI)
115 return STM32_HSI_FREQ;
116 #else
117 __ASSERT(0, "No SYSCLK Source configured");
118 return 0;
119 #endif
120
121 }
122
123 /** @brief Verifies clock is part of active clock configuration */
enabled_clock(uint32_t src_clk)124 int enabled_clock(uint32_t src_clk)
125 {
126 if ((src_clk == STM32_SRC_SYSCLK) ||
127 (src_clk == STM32_SRC_HCLK) ||
128 (src_clk == STM32_SRC_PCLK1) ||
129 (src_clk == STM32_SRC_PCLK2) ||
130 (src_clk == STM32_SRC_PCLK3) ||
131 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
132 ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
133 ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
134 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
135 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
136 ((src_clk == STM32_SRC_MSIS) && IS_ENABLED(STM32_MSIS_ENABLED)) ||
137 ((src_clk == STM32_SRC_MSIK) && IS_ENABLED(STM32_MSIK_ENABLED)) ||
138 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
139 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||
140 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||
141 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
142 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
143 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
144 ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
145 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
146 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
147 return 0;
148 }
149
150 return -ENOTSUP;
151 }
152
stm32_clock_control_on(const struct device * dev,clock_control_subsys_t sub_system)153 static inline int stm32_clock_control_on(const struct device *dev,
154 clock_control_subsys_t sub_system)
155 {
156 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
157 volatile int temp;
158
159 ARG_UNUSED(dev);
160
161 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
162 /* Attempt to toggle a wrong periph clock bit */
163 return -ENOTSUP;
164 }
165
166 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
167 pclken->enr);
168 /* Delay after enabling the clock, to allow it to become active */
169 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
170 UNUSED(temp);
171
172 return 0;
173 }
174
stm32_clock_control_off(const struct device * dev,clock_control_subsys_t sub_system)175 static inline int stm32_clock_control_off(const struct device *dev,
176 clock_control_subsys_t sub_system)
177 {
178 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
179
180 ARG_UNUSED(dev);
181
182 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
183 /* Attempt to toggle a wrong periph clock bit */
184 return -ENOTSUP;
185 }
186
187 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
188 pclken->enr);
189
190 return 0;
191 }
192
stm32_clock_control_configure(const struct device * dev,clock_control_subsys_t sub_system,void * data)193 static inline int stm32_clock_control_configure(const struct device *dev,
194 clock_control_subsys_t sub_system,
195 void *data)
196 {
197 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
198 int err;
199
200 ARG_UNUSED(dev);
201 ARG_UNUSED(data);
202
203 err = enabled_clock(pclken->bus);
204 if (err < 0) {
205 /* Attempt to configure a src clock not available or not valid */
206 return err;
207 }
208
209 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
210 STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
211 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
212 STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
213
214 return 0;
215 }
216
stm32_clock_control_get_subsys_rate(const struct device * dev,clock_control_subsys_t sys,uint32_t * rate)217 static int stm32_clock_control_get_subsys_rate(const struct device *dev,
218 clock_control_subsys_t sys,
219 uint32_t *rate)
220 {
221 struct stm32_pclken *pclken = (struct stm32_pclken *)(sys);
222
223 /*
224 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
225 * SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
226 * since it will be updated after clock configuration and hence
227 * more likely to contain actual clock speed
228 */
229 uint32_t ahb_clock = SystemCoreClock;
230 uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
231 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
232 uint32_t apb3_clock = get_bus_clock(ahb_clock, STM32_APB3_PRESCALER);
233
234 ARG_UNUSED(dev);
235
236 switch (pclken->bus) {
237 case STM32_CLOCK_BUS_AHB1:
238 case STM32_CLOCK_BUS_AHB2:
239 case STM32_CLOCK_BUS_AHB2_2:
240 case STM32_CLOCK_BUS_AHB3:
241 case STM32_SRC_HCLK:
242 *rate = ahb_clock;
243 break;
244 case STM32_CLOCK_BUS_APB1:
245 case STM32_CLOCK_BUS_APB1_2:
246 case STM32_SRC_PCLK1:
247 *rate = apb1_clock;
248 break;
249 case STM32_CLOCK_BUS_APB2:
250 case STM32_SRC_PCLK2:
251 *rate = apb2_clock;
252 break;
253 case STM32_CLOCK_BUS_APB3:
254 case STM32_SRC_PCLK3:
255 *rate = apb3_clock;
256 break;
257 case STM32_SRC_SYSCLK:
258 *rate = get_sysclk_frequency();
259 break;
260 #if defined(STM32_HSI_ENABLED)
261 case STM32_SRC_HSI16:
262 *rate = STM32_HSI_FREQ;
263 break;
264 #endif /* STM32_HSI_ENABLED */
265 #if defined(STM32_MSIS_ENABLED)
266 case STM32_SRC_MSIS:
267 *rate = get_msis_frequency();
268 break;
269 #endif /* STM32_MSIS_ENABLED */
270 #if defined(STM32_MSIK_ENABLED)
271 case STM32_SRC_MSIK:
272 *rate = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSIRANGESEL_RUN,
273 STM32_MSIK_RANGE << RCC_ICSCR1_MSIKRANGE_Pos);
274 break;
275 #endif /* STM32_MSIK_ENABLED */
276 #if defined(STM32_HSE_ENABLED)
277 case STM32_SRC_HSE:
278 *rate = STM32_HSE_FREQ;
279 break;
280 #endif /* STM32_HSE_ENABLED */
281 #if defined(STM32_LSE_ENABLED)
282 case STM32_SRC_LSE:
283 *rate = STM32_LSE_FREQ;
284 break;
285 #endif /* STM32_LSE_ENABLED */
286 #if defined(STM32_LSI_ENABLED)
287 case STM32_SRC_LSI:
288 *rate = STM32_LSI_FREQ;
289 break;
290 #endif /* STM32_LSI_ENABLED */
291 #if defined(STM32_HSI48_ENABLED)
292 case STM32_SRC_HSI48:
293 *rate = STM32_HSI48_FREQ;
294 break;
295 #endif /* STM32_HSI48_ENABLED */
296 #if defined(STM32_PLL_ENABLED)
297 case STM32_SRC_PLL1_P:
298 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID),
299 STM32_PLL_M_DIVISOR,
300 STM32_PLL_N_MULTIPLIER,
301 STM32_PLL_P_DIVISOR);
302 break;
303 case STM32_SRC_PLL1_Q:
304 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID),
305 STM32_PLL_M_DIVISOR,
306 STM32_PLL_N_MULTIPLIER,
307 STM32_PLL_Q_DIVISOR);
308 break;
309 case STM32_SRC_PLL1_R:
310 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID),
311 STM32_PLL_M_DIVISOR,
312 STM32_PLL_N_MULTIPLIER,
313 STM32_PLL_R_DIVISOR);
314 break;
315 #endif /* STM32_PLL_ENABLED */
316 #if defined(STM32_PLL2_ENABLED)
317 case STM32_SRC_PLL2_P:
318 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID),
319 STM32_PLL2_M_DIVISOR,
320 STM32_PLL2_N_MULTIPLIER,
321 STM32_PLL2_P_DIVISOR);
322 break;
323 case STM32_SRC_PLL2_Q:
324 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID),
325 STM32_PLL2_M_DIVISOR,
326 STM32_PLL2_N_MULTIPLIER,
327 STM32_PLL2_Q_DIVISOR);
328 break;
329 case STM32_SRC_PLL2_R:
330 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID),
331 STM32_PLL2_M_DIVISOR,
332 STM32_PLL2_N_MULTIPLIER,
333 STM32_PLL2_R_DIVISOR);
334 break;
335 #endif /* STM32_PLL2_ENABLED */
336 #if defined(STM32_PLL3_ENABLED)
337 case STM32_SRC_PLL3_P:
338 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID),
339 STM32_PLL3_M_DIVISOR,
340 STM32_PLL3_N_MULTIPLIER,
341 STM32_PLL3_P_DIVISOR);
342 break;
343 case STM32_SRC_PLL3_Q:
344 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID),
345 STM32_PLL3_M_DIVISOR,
346 STM32_PLL3_N_MULTIPLIER,
347 STM32_PLL3_Q_DIVISOR);
348 break;
349 case STM32_SRC_PLL3_R:
350 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID),
351 STM32_PLL3_M_DIVISOR,
352 STM32_PLL3_N_MULTIPLIER,
353 STM32_PLL3_R_DIVISOR);
354 break;
355 #endif /* STM32_PLL3_ENABLED */
356 default:
357 return -ENOTSUP;
358 }
359
360 if (pclken->div) {
361 *rate /= (pclken->div + 1);
362 }
363
364 return 0;
365 }
366
stm32_clock_control_get_status(const struct device * dev,clock_control_subsys_t sub_system)367 static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
368 clock_control_subsys_t sub_system)
369 {
370 struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
371
372 ARG_UNUSED(dev);
373
374 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
375 /* Gated clocks */
376 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
377 == pclken->enr) {
378 return CLOCK_CONTROL_STATUS_ON;
379 } else {
380 return CLOCK_CONTROL_STATUS_OFF;
381 }
382 } else {
383 /* Domain clock sources */
384 if (enabled_clock(pclken->bus) == 0) {
385 return CLOCK_CONTROL_STATUS_ON;
386 } else {
387 return CLOCK_CONTROL_STATUS_OFF;
388 }
389 }
390 }
391
392 static DEVICE_API(clock_control, stm32_clock_control_api) = {
393 .on = stm32_clock_control_on,
394 .off = stm32_clock_control_off,
395 .get_rate = stm32_clock_control_get_subsys_rate,
396 .get_status = stm32_clock_control_get_status,
397 .configure = stm32_clock_control_configure,
398 };
399
400 __unused
get_vco_input_range(uint32_t m_div,uint32_t * range,size_t pll_id)401 static int get_vco_input_range(uint32_t m_div, uint32_t *range, size_t pll_id)
402 {
403 uint32_t vco_freq;
404
405 vco_freq = get_pllsrc_frequency(pll_id) / m_div;
406
407 if (MHZ(4) <= vco_freq && vco_freq <= MHZ(8)) {
408 *range = LL_RCC_PLLINPUTRANGE_4_8;
409 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {
410 *range = LL_RCC_PLLINPUTRANGE_8_16;
411 } else {
412 return -ERANGE;
413 }
414
415 return 0;
416 }
417
set_regu_voltage(uint32_t hclk_freq)418 static void set_regu_voltage(uint32_t hclk_freq)
419 {
420 if (hclk_freq < MHZ(25)) {
421 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE4);
422 } else if (hclk_freq < MHZ(55)) {
423 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
424 } else if (hclk_freq < MHZ(110)) {
425 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
426 } else {
427 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
428 }
429 while (LL_PWR_IsActiveFlag_VOS() == 0) {
430 }
431 }
432
433 #if defined(STM32_PLL_ENABLED)
434 /*
435 * Dynamic voltage scaling:
436 * Enable the Booster mode before enabling then PLL for sysclock above 55MHz
437 * The goal of this function is to set the epod prescaler, so that epod clock freq
438 * is between 4MHz and 16MHz.
439 * Up to now only MSI as PLL1 source clock can be > 16MHz, requiring a epod prescaler > 1
440 * For HSI16, epod prescaler is default (div1, not divided).
441 * Once HSE is > 16MHz, the epod prescaler would also be also required.
442 */
set_epod_booster(void)443 static void set_epod_booster(void)
444 {
445 /* Reset Epod Prescaler in case it was set earlier with another DIV value */
446 LL_PWR_DisableEPODBooster();
447 while (LL_PWR_IsActiveFlag_BOOST() == 1) {
448 }
449
450 LL_RCC_SetPll1EPodPrescaler(LL_RCC_PLL1MBOOST_DIV_1);
451
452 if (MHZ(55) <= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
453 /*
454 * Set EPOD clock prescaler based on PLL1 input freq
455 * (MSI/PLLM or HSE/PLLM when HSE is > 16MHz
456 * Booster clock frequency should be between 4 and 16MHz
457 * This is done in following steps:
458 * Read MSI Frequency or HSE oscillaor freq
459 * Divide PLL1 input freq (MSI/PLL or HSE/PLLM)
460 * by the targeted freq (8MHz).
461 * Make sure value is not higher than 16
462 * Shift in the register space (/2)
463 */
464 int tmp;
465
466 if (IS_ENABLED(STM32_PLL_SRC_MSIS)) {
467 tmp = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSIRANGESEL_RUN,
468 STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
469 } else if (IS_ENABLED(STM32_PLL_SRC_HSE) && (MHZ(16) < STM32_HSE_FREQ)) {
470 tmp = STM32_HSE_FREQ;
471 } else {
472 return;
473 }
474
475 tmp = MIN(tmp / STM32_PLL_M_DIVISOR / 8000000, 16);
476 tmp = tmp / 2;
477
478 /* Configure the epod clock frequency between 4 and 16 MHz */
479 LL_RCC_SetPll1EPodPrescaler(tmp << RCC_PLL1CFGR_PLL1MBOOST_Pos);
480
481 /* Enable EPOD booster and wait for booster ready flag set */
482 LL_PWR_EnableEPODBooster();
483 while (LL_PWR_IsActiveFlag_BOOST() == 0) {
484 }
485 }
486 }
487 #endif /* STM32_PLL_ENABLED */
488
489 __unused
clock_switch_to_hsi(void)490 static void clock_switch_to_hsi(void)
491 {
492 /* Enable HSI if not enabled */
493 if (LL_RCC_HSI_IsReady() != 1) {
494 /* Enable HSI */
495 LL_RCC_HSI_Enable();
496 while (LL_RCC_HSI_IsReady() != 1) {
497 /* Wait for HSI ready */
498 }
499 }
500
501 /* Set HSI as SYSCLCK source */
502 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
503 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
504 }
505
506 LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
507 }
508
509 __unused
set_up_plls(void)510 static int set_up_plls(void)
511 {
512 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || \
513 defined(STM32_PLL3_ENABLED)
514 int r;
515 uint32_t vco_input_range;
516 #endif
517
518 #if defined(STM32_PLL_ENABLED)
519 /*
520 * Switch to HSI and disable the PLL before configuration.
521 * (Switching to HSI makes sure we have a SYSCLK source in
522 * case we're currently running from the PLL we're about to
523 * turn off and reconfigure.)
524 */
525 if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
526 clock_switch_to_hsi();
527 }
528
529 LL_RCC_PLL1_Disable();
530
531 /* Configure PLL source : Can be HSE, HSI, MSIS */
532 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
533 /* Main PLL configuration and activation */
534 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_HSE);
535 } else if (IS_ENABLED(STM32_PLL_SRC_MSIS)) {
536 /* Main PLL configuration and activation */
537 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_MSIS);
538 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
539 /* Main PLL configuration and activation */
540 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_HSI);
541 } else {
542 return -ENOTSUP;
543 }
544
545 /*
546 * Configure the EPOD booster
547 * before increasing the system clock freq
548 * and after pll clock source is set
549 */
550 set_epod_booster();
551
552 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID);
553 if (r < 0) {
554 return r;
555 }
556
557 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR);
558
559 /* Set VCO Input before enabling the PLL, depends on freq used for PLL1 */
560 LL_RCC_PLL1_SetVCOInputRange(vco_input_range);
561
562 LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
563
564 LL_RCC_PLL1FRACN_Disable();
565 if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
566 LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
567 LL_RCC_PLL1FRACN_Enable();
568 }
569
570 if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
571 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
572 LL_RCC_PLL1_EnableDomain_SAI();
573 }
574
575 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
576 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
577 LL_RCC_PLL1_EnableDomain_48M();
578 }
579
580 if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
581 __ASSERT_NO_MSG((STM32_PLL_R_DIVISOR == 1) ||
582 (STM32_PLL_R_DIVISOR % 2 == 0));
583 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
584 LL_RCC_PLL1_EnableDomain_SYS();
585 }
586
587 LL_RCC_PLL1_Enable();
588 while (LL_RCC_PLL1_IsReady() != 1U) {
589 }
590 #else
591 /* Init PLL source to None */
592 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_NONE);
593 #endif /* STM32_PLL_ENABLED */
594
595 #if defined(STM32_PLL2_ENABLED)
596 /* Configure PLL2 source */
597 if (IS_ENABLED(STM32_PLL2_SRC_HSE)) {
598 LL_RCC_PLL2_SetSource(LL_RCC_PLL2SOURCE_HSE);
599 } else if (IS_ENABLED(STM32_PLL2_SRC_MSIS)) {
600 LL_RCC_PLL2_SetSource(LL_RCC_PLL2SOURCE_MSIS);
601 } else if (IS_ENABLED(STM32_PLL2_SRC_HSI)) {
602 LL_RCC_PLL2_SetSource(LL_RCC_PLL2SOURCE_HSI);
603 } else {
604 return -ENOTSUP;
605 }
606
607 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID);
608 if (r < 0) {
609 return r;
610 }
611
612 LL_RCC_PLL2_SetDivider(STM32_PLL2_M_DIVISOR);
613
614 LL_RCC_PLL2_SetVCOInputRange(vco_input_range);
615
616 LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
617
618 LL_RCC_PLL2FRACN_Disable();
619 if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) {
620 LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE);
621 LL_RCC_PLL2FRACN_Enable();
622 }
623
624 if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
625 LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
626 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
627 }
628
629 if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) {
630 LL_RCC_PLL2_SetQ(STM32_PLL2_Q_DIVISOR);
631 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
632 }
633
634 if (IS_ENABLED(STM32_PLL2_R_ENABLED)) {
635 LL_RCC_PLL2_SetR(STM32_PLL2_R_DIVISOR);
636 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
637 }
638
639 LL_RCC_PLL2_Enable();
640 while (LL_RCC_PLL2_IsReady() != 1U) {
641 }
642 #else
643 /* Init PLL2 source to None */
644 LL_RCC_PLL2_SetSource(LL_RCC_PLL2SOURCE_NONE);
645 #endif /* STM32_PLL2_ENABLED */
646
647 #if defined(STM32_PLL3_ENABLED)
648 /* Configure PLL3 source */
649 if (IS_ENABLED(STM32_PLL3_SRC_HSE)) {
650 LL_RCC_PLL3_SetSource(LL_RCC_PLL3SOURCE_HSE);
651 } else if (IS_ENABLED(STM32_PLL3_SRC_MSIS)) {
652 LL_RCC_PLL3_SetSource(LL_RCC_PLL3SOURCE_MSIS);
653 } else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) {
654 LL_RCC_PLL3_SetSource(LL_RCC_PLL3SOURCE_HSI);
655 } else {
656 return -ENOTSUP;
657 }
658
659 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID);
660 if (r < 0) {
661 return r;
662 }
663
664 LL_RCC_PLL3_SetDivider(STM32_PLL3_M_DIVISOR);
665
666 LL_RCC_PLL3_SetVCOInputRange(vco_input_range);
667
668 LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
669
670 LL_RCC_PLL3FRACN_Disable();
671 if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) {
672 LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE);
673 LL_RCC_PLL3FRACN_Enable();
674 }
675
676 if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
677 LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
678 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
679 }
680
681 if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
682 LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
683 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
684 }
685
686 if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
687 LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
688 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
689 }
690
691 LL_RCC_PLL3_Enable();
692 while (LL_RCC_PLL3_IsReady() != 1U) {
693 }
694 #else
695 /* Init PLL3 source to None */
696 LL_RCC_PLL3_SetSource(LL_RCC_PLL3SOURCE_NONE);
697 #endif /* STM32_PLL3_ENABLED */
698
699 return 0;
700 }
701
set_up_fixed_clock_sources(void)702 static void set_up_fixed_clock_sources(void)
703 {
704
705 if (IS_ENABLED(STM32_HSE_ENABLED)) {
706 /* Check if need to enable HSE bypass feature or not */
707 if (IS_ENABLED(STM32_HSE_BYPASS)) {
708 LL_RCC_HSE_EnableBypass();
709 } else {
710 LL_RCC_HSE_DisableBypass();
711 }
712
713 /* Enable HSE */
714 LL_RCC_HSE_Enable();
715 while (LL_RCC_HSE_IsReady() != 1) {
716 /* Wait for HSE ready */
717 }
718 }
719
720 if (IS_ENABLED(STM32_HSI_ENABLED)) {
721 /* Enable HSI if not enabled */
722 if (LL_RCC_HSI_IsReady() != 1) {
723 /* Enable HSI */
724 LL_RCC_HSI_Enable();
725 while (LL_RCC_HSI_IsReady() != 1) {
726 /* Wait for HSI ready */
727 }
728 }
729 }
730
731 if (IS_ENABLED(STM32_LSE_ENABLED)) {
732 /* Enable the power interface clock */
733 LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
734
735 if (!LL_PWR_IsEnabledBkUpAccess()) {
736 /* Enable write access to Backup domain */
737 LL_PWR_EnableBkUpAccess();
738 while (!LL_PWR_IsEnabledBkUpAccess()) {
739 /* Wait for Backup domain access */
740 }
741 }
742
743 /* Configure driving capability */
744 LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
745
746 if (IS_ENABLED(STM32_LSE_BYPASS)) {
747 /* Configure LSE bypass */
748 LL_RCC_LSE_EnableBypass();
749 }
750
751 /* Enable LSE Oscillator */
752 LL_RCC_LSE_Enable();
753 /* Wait for LSE ready */
754 while (!LL_RCC_LSE_IsReady()) {
755 }
756
757 /* Enable LSESYS additionally */
758 LL_RCC_LSE_EnablePropagation();
759 /* Wait till LSESYS is ready */
760 while (!LL_RCC_LSESYS_IsReady()) {
761 }
762
763 LL_PWR_DisableBkUpAccess();
764 }
765
766 if (IS_ENABLED(STM32_MSIS_ENABLED)) {
767 /* Set MSIS Range */
768 LL_RCC_MSI_EnableRangeSelection();
769
770 LL_RCC_MSIS_SetRange(STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
771
772 if (IS_ENABLED(STM32_MSIS_PLL_MODE)) {
773 __ASSERT(STM32_LSE_ENABLED,
774 "MSIS Hardware auto calibration needs LSE clock activation");
775 /* Enable MSI hardware auto calibration */
776 LL_RCC_SetMSIPLLMode(LL_RCC_PLLMODE_MSIS);
777 LL_RCC_MSI_EnablePLLMode();
778 }
779
780 /* Enable MSIS */
781 LL_RCC_MSIS_Enable();
782
783 /* Wait till MSIS is ready */
784 while (LL_RCC_MSIS_IsReady() != 1) {
785 }
786 }
787
788 if (IS_ENABLED(STM32_MSIK_ENABLED)) {
789 /* Set MSIK Range */
790 LL_RCC_MSI_EnableRangeSelection();
791
792 LL_RCC_MSIK_SetRange(STM32_MSIK_RANGE << RCC_ICSCR1_MSIKRANGE_Pos);
793
794 if (IS_ENABLED(STM32_MSIK_PLL_MODE)) {
795 __ASSERT(STM32_LSE_ENABLED,
796 "MSIK Hardware auto calibration needs LSE clock activation");
797 /* Enable MSI hardware auto calibration */
798 LL_RCC_SetMSIPLLMode(LL_RCC_PLLMODE_MSIK);
799 LL_RCC_MSI_EnablePLLMode();
800 }
801
802 if (IS_ENABLED(STM32_MSIS_ENABLED)) {
803 __ASSERT((STM32_MSIK_PLL_MODE == STM32_MSIS_PLL_MODE),
804 "Please check MSIS/MSIK config consistency");
805 }
806
807 /* Enable MSIK */
808 LL_RCC_MSIK_Enable();
809
810 /* Wait till MSIK is ready */
811 while (LL_RCC_MSIK_IsReady() != 1) {
812 }
813 }
814
815 if (IS_ENABLED(STM32_LSI_ENABLED)) {
816 if (!LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR)) {
817 /* Enable the power interface clock */
818 LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
819 }
820
821 if (!LL_PWR_IsEnabledBkUpAccess()) {
822 /* Enable write access to Backup domain */
823 LL_PWR_EnableBkUpAccess();
824 while (!LL_PWR_IsEnabledBkUpAccess()) {
825 /* Wait for Backup domain access */
826 }
827 }
828
829 /* Enable LSI oscillator */
830 LL_RCC_LSI_Enable();
831 while (LL_RCC_LSI_IsReady() != 1) {
832 }
833
834 LL_PWR_DisableBkUpAccess();
835 }
836
837 if (IS_ENABLED(STM32_HSI48_ENABLED)) {
838 LL_RCC_HSI48_Enable();
839 while (LL_RCC_HSI48_IsReady() != 1) {
840 }
841 }
842 }
843
stm32_clock_control_init(const struct device * dev)844 int stm32_clock_control_init(const struct device *dev)
845 {
846 uint32_t old_hclk_freq;
847 int r;
848
849 ARG_UNUSED(dev);
850
851 /* Current hclk value */
852 old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
853
854 /* Set voltage regulator to comply with targeted system frequency */
855 set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
856
857 /* Set flash latency */
858 /* If freq increases, set flash latency before any clock setting */
859 if (old_hclk_freq < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
860 LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
861 }
862
863 /* Set up individual enabled clocks */
864 set_up_fixed_clock_sources();
865
866 /* Set up PLLs */
867 r = set_up_plls();
868 if (r < 0) {
869 return r;
870 }
871
872 /* Set peripheral buses prescalers */
873 LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
874 LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
875 LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
876 LL_RCC_SetAPB3Prescaler(apb3_prescaler(STM32_APB3_PRESCALER));
877
878 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
879 /* Set PLL1 as System Clock Source */
880 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
881 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
882 }
883 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
884 /* Set HSE as SYSCLCK source */
885 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
886 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
887 }
888 } else if (IS_ENABLED(STM32_SYSCLK_SRC_MSIS)) {
889 /* Set MSIS as SYSCLCK source */
890 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS);
891 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) {
892 }
893 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
894 /* Set HSI as SYSCLCK source */
895 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
896 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
897 }
898 } else {
899 return -ENOTSUP;
900 }
901
902 /* Set FLASH latency */
903 /* If freq not increased, set flash latency after all clock setting */
904 if (old_hclk_freq >= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
905 LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
906 }
907
908 /* Update CMSIS variable */
909 SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
910
911 return 0;
912 }
913
914 /**
915 * @brief RCC device, note that priority is intentionally set to 1 so
916 * that the device init runs just after SOC init
917 */
918 DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
919 stm32_clock_control_init,
920 NULL,
921 NULL, NULL,
922 PRE_KERNEL_1,
923 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
924 &stm32_clock_control_api);
925
