1# Copyright (c) 2024 STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  PLL node binding for STM32H7RS devices
6
7  It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
8
9  These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
10  an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
11  clock in this acceptable range.
12
13  Each PLL can have up to 5 output clocks and for each output clock, the
14  frequency can be computed with the following formulae:
15
16    f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
17    f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
18    f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
19    f(PLL_Sx) = f(VCOx clock) / PLLSx   -> pllx_s_ck
20    f(PLL_Tx) = f(VCOx clock) / PLLTx   -> pllx_t_ck (only for PLL2)
21
22      with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
23
24
25compatible: "st,stm32h7rs-pll-clock"
26
27include: st,stm32h7-pll-clock.yaml
28
29properties:
30  div-s:
31    type: int
32    description: |
33        PLL division factor for pllx_s_ck : valid for PLL1, 2, 3
34        Valid range: 1 - 8
35
36  div-t:
37    type: int
38    description: |
39        PLL division factor for pllx_t_ck : valid for PLL2
40        Valid range: 1 - 8
41