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/Zephyr-latest/dts/bindings/display/
Dftdi,ft800.yaml15 pclk:
19 The value to divide the main clock by for PCLK. If the
20 typical main clock was 48MHz and this value is 5, the PCLK
23 pclk-pol:
27 Polarity of PCLK. If it is set to zero, PCLK polarity is on
28 the rising edge. If it is set to one, PCLK polarity is on
35 Controls the transition of RGB signals with PCLK active clock
37 following the active edge of PCLK. When set to 1, R[7:2]
38 changes a PCLK clock early and B[7:2] a PCLK clock later,
83 description: Number of PCLK cycles per visible part of horizontal line
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi114 compatible = "renesas,ra-cgc-pclk-block";
124 compatible = "renesas,ra-cgc-pclk";
132 compatible = "renesas,ra-cgc-pclk";
139 compatible = "renesas,ra-cgc-pclk";
146 compatible = "renesas,ra-cgc-pclk";
153 compatible = "renesas,ra-cgc-pclk";
160 compatible = "renesas,ra-cgc-pclk";
167 compatible = "renesas,ra-cgc-pclk";
174 compatible = "renesas,ra-cgc-pclk";
187 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa8m1xh.dtsi117 compatible = "renesas,ra-cgc-pclk-block";
127 compatible = "renesas,ra-cgc-pclk";
135 compatible = "renesas,ra-cgc-pclk";
142 compatible = "renesas,ra-cgc-pclk";
149 compatible = "renesas,ra-cgc-pclk";
156 compatible = "renesas,ra-cgc-pclk";
163 compatible = "renesas,ra-cgc-pclk";
170 compatible = "renesas,ra-cgc-pclk";
177 compatible = "renesas,ra-cgc-pclk";
190 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa8d1xh.dtsi147 compatible = "renesas,ra-cgc-pclk-block";
157 compatible = "renesas,ra-cgc-pclk";
165 compatible = "renesas,ra-cgc-pclk";
172 compatible = "renesas,ra-cgc-pclk";
179 compatible = "renesas,ra-cgc-pclk";
186 compatible = "renesas,ra-cgc-pclk";
193 compatible = "renesas,ra-cgc-pclk";
200 compatible = "renesas,ra-cgc-pclk";
207 compatible = "renesas,ra-cgc-pclk";
220 compatible = "renesas,ra-cgc-pclk";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2l1xxxxfp.dtsi49 compatible = "renesas,ra-cgc-pclk-block";
59 compatible = "renesas,ra-cgc-pclk";
67 compatible = "renesas,ra-cgc-pclk";
74 compatible = "renesas,ra-cgc-pclk";
81 compatible = "renesas,ra-cgc-pclk";
Dr7fa2a1xh.dtsi140 compatible = "renesas,ra-cgc-pclk-block";
150 compatible = "renesas,ra-cgc-pclk";
158 compatible = "renesas,ra-cgc-pclk";
165 compatible = "renesas,ra-cgc-pclk";
172 compatible = "renesas,ra-cgc-pclk";
179 compatible = "renesas,ra-cgc-pclk";
185 compatible = "renesas,ra-cgc-pclk";
191 compatible = "renesas,ra-cgc-pclk";
/Zephyr-latest/dts/bindings/clock/
Drenesas,ra-cgc-pclk-block.yaml4 description: Renesas RA Clock Control node pclk block
6 compatible: "renesas,ra-cgc-pclk-block"
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4e2b93cfm.dtsi146 compatible = "renesas,ra-cgc-pclk-block";
156 compatible = "renesas,ra-cgc-pclk";
164 compatible = "renesas,ra-cgc-pclk";
171 compatible = "renesas,ra-cgc-pclk";
178 compatible = "renesas,ra-cgc-pclk";
185 compatible = "renesas,ra-cgc-pclk";
192 compatible = "renesas,ra-cgc-pclk";
199 compatible = "renesas,ra-cgc-pclk";
205 compatible = "renesas,ra-cgc-pclk";
211 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa4w1ad2cng.dtsi108 compatible = "renesas,ra-cgc-pclk-block";
118 compatible = "renesas,ra-cgc-pclk";
126 compatible = "renesas,ra-cgc-pclk";
133 compatible = "renesas,ra-cgc-pclk";
140 compatible = "renesas,ra-cgc-pclk";
147 compatible = "renesas,ra-cgc-pclk";
154 compatible = "renesas,ra-cgc-pclk";
161 compatible = "renesas,ra-cgc-pclk";
167 compatible = "renesas,ra-cgc-pclk";
Dr7fa4e10x.dtsi128 compatible = "renesas,ra-cgc-pclk-block";
138 compatible = "renesas,ra-cgc-pclk";
146 compatible = "renesas,ra-cgc-pclk";
153 compatible = "renesas,ra-cgc-pclk";
160 compatible = "renesas,ra-cgc-pclk";
167 compatible = "renesas,ra-cgc-pclk";
174 compatible = "renesas,ra-cgc-pclk";
181 compatible = "renesas,ra-cgc-pclk";
187 compatible = "renesas,ra-cgc-pclk";
Dr7fa4m1ax.dtsi174 compatible = "renesas,ra-cgc-pclk-block";
184 compatible = "renesas,ra-cgc-pclk";
192 compatible = "renesas,ra-cgc-pclk";
199 compatible = "renesas,ra-cgc-pclk";
206 compatible = "renesas,ra-cgc-pclk";
213 compatible = "renesas,ra-cgc-pclk";
220 compatible = "renesas,ra-cgc-pclk";
227 compatible = "renesas,ra-cgc-pclk";
233 compatible = "renesas,ra-cgc-pclk";
Dr7fa4m2ax.dtsi206 compatible = "renesas,ra-cgc-pclk-block";
216 compatible = "renesas,ra-cgc-pclk";
224 compatible = "renesas,ra-cgc-pclk";
231 compatible = "renesas,ra-cgc-pclk";
238 compatible = "renesas,ra-cgc-pclk";
245 compatible = "renesas,ra-cgc-pclk";
252 compatible = "renesas,ra-cgc-pclk";
259 compatible = "renesas,ra-cgc-pclk";
265 compatible = "renesas,ra-cgc-pclk";
Dr7fa4m3ax.dtsi216 compatible = "renesas,ra-cgc-pclk-block";
226 compatible = "renesas,ra-cgc-pclk";
234 compatible = "renesas,ra-cgc-pclk";
241 compatible = "renesas,ra-cgc-pclk";
248 compatible = "renesas,ra-cgc-pclk";
255 compatible = "renesas,ra-cgc-pclk";
262 compatible = "renesas,ra-cgc-pclk";
269 compatible = "renesas,ra-cgc-pclk";
275 compatible = "renesas,ra-cgc-pclk";
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6e2bx.dtsi144 compatible = "renesas,ra-cgc-pclk-block";
154 compatible = "renesas,ra-cgc-pclk";
162 compatible = "renesas,ra-cgc-pclk";
169 compatible = "renesas,ra-cgc-pclk";
176 compatible = "renesas,ra-cgc-pclk";
183 compatible = "renesas,ra-cgc-pclk";
190 compatible = "renesas,ra-cgc-pclk";
197 compatible = "renesas,ra-cgc-pclk";
203 compatible = "renesas,ra-cgc-pclk";
209 compatible = "renesas,ra-cgc-pclk";
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Dr7fa6m1ad3cfp.dtsi98 compatible = "renesas,ra-cgc-pclk-block";
108 compatible = "renesas,ra-cgc-pclk";
116 compatible = "renesas,ra-cgc-pclk";
123 compatible = "renesas,ra-cgc-pclk";
130 compatible = "renesas,ra-cgc-pclk";
137 compatible = "renesas,ra-cgc-pclk";
144 compatible = "renesas,ra-cgc-pclk";
157 compatible = "renesas,ra-cgc-pclk";
164 compatible = "renesas,ra-cgc-pclk";
171 compatible = "renesas,ra-cgc-pclk";
Dr7fa6m2ax.dtsi130 compatible = "renesas,ra-cgc-pclk-block";
140 compatible = "renesas,ra-cgc-pclk";
148 compatible = "renesas,ra-cgc-pclk";
155 compatible = "renesas,ra-cgc-pclk";
162 compatible = "renesas,ra-cgc-pclk";
169 compatible = "renesas,ra-cgc-pclk";
176 compatible = "renesas,ra-cgc-pclk";
189 compatible = "renesas,ra-cgc-pclk";
196 compatible = "renesas,ra-cgc-pclk";
203 compatible = "renesas,ra-cgc-pclk";
Dr7fa6m3ax.dtsi189 compatible = "renesas,ra-cgc-pclk-block";
199 compatible = "renesas,ra-cgc-pclk";
207 compatible = "renesas,ra-cgc-pclk";
214 compatible = "renesas,ra-cgc-pclk";
221 compatible = "renesas,ra-cgc-pclk";
228 compatible = "renesas,ra-cgc-pclk";
235 compatible = "renesas,ra-cgc-pclk";
248 compatible = "renesas,ra-cgc-pclk";
255 compatible = "renesas,ra-cgc-pclk";
262 compatible = "renesas,ra-cgc-pclk";
Dr7fa6e10x.dtsi185 compatible = "renesas,ra-cgc-pclk-block";
195 compatible = "renesas,ra-cgc-pclk";
203 compatible = "renesas,ra-cgc-pclk";
210 compatible = "renesas,ra-cgc-pclk";
217 compatible = "renesas,ra-cgc-pclk";
224 compatible = "renesas,ra-cgc-pclk";
231 compatible = "renesas,ra-cgc-pclk";
238 compatible = "renesas,ra-cgc-pclk";
244 compatible = "renesas,ra-cgc-pclk";
Dr7fa6m5xh.dtsi344 compatible = "renesas,ra-cgc-pclk-block";
354 compatible = "renesas,ra-cgc-pclk";
362 compatible = "renesas,ra-cgc-pclk";
369 compatible = "renesas,ra-cgc-pclk";
376 compatible = "renesas,ra-cgc-pclk";
383 compatible = "renesas,ra-cgc-pclk";
390 compatible = "renesas,ra-cgc-pclk";
403 compatible = "renesas,ra-cgc-pclk";
410 compatible = "renesas,ra-cgc-pclk";
416 compatible = "renesas,ra-cgc-pclk";
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Dr7fa6m4ax.dtsi292 compatible = "renesas,ra-cgc-pclk-block";
302 compatible = "renesas,ra-cgc-pclk";
310 compatible = "renesas,ra-cgc-pclk";
317 compatible = "renesas,ra-cgc-pclk";
324 compatible = "renesas,ra-cgc-pclk";
331 compatible = "renesas,ra-cgc-pclk";
338 compatible = "renesas,ra-cgc-pclk";
351 compatible = "renesas,ra-cgc-pclk";
358 compatible = "renesas,ra-cgc-pclk";
364 compatible = "renesas,ra-cgc-pclk";
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dsoc.h14 /* On FU740, peripherals are clocked by PCLK. */
16 DT_PROP(DT_NODELABEL(pclk), clock_frequency)
/Zephyr-latest/dts/bindings/video/
Dnxp,video-smartdma.yaml25 pclk-pin:
29 GPIO0 pin index to use for PCLK input. Only pins 0-15 may be used.
/Zephyr-latest/boards/shields/ftdi_vm800c/
Dftdi_vm800c.overlay21 pclk = <5>;
22 pclk-pol = <1>;
/Zephyr-latest/drivers/watchdog/
Dwdt_wwdgt_gd32.c47 * timeout = pclk * INTERNAL_DIVIDER * (2^prescaler_exp) * (count + 1)
49 * count = (timeout * pclk / INTERNAL_DIVIDER * (2^prescaler_exp) ) - 1
57 uint32_t pclk; in gd32_wwdgt_calc_ticks() local
61 &pclk); in gd32_wwdgt_calc_ticks()
63 return ((timeout * pclk) in gd32_wwdgt_calc_ticks()
/Zephyr-latest/drivers/pwm/
Dpwm_rpi_pico.c55 uint32_t pclk; in pwm_rpi_get_cycles_per_sec() local
64 ret = clock_control_get_rate(cfg->clk_dev, cfg->clk_id, &pclk); in pwm_rpi_get_cycles_per_sec()
65 if (ret < 0 || pclk == 0) { in pwm_rpi_get_cycles_per_sec()
70 *cycles = pclk; in pwm_rpi_get_cycles_per_sec()
75 *cycles = (uint64_t)pclk * 16 / in pwm_rpi_get_cycles_per_sec()

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