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/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1024dag5a-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
26 bias-disable;
27 drive-strength = "r0-6";
28 slew-rate = "fast";
29 nxp,speed = "50-mhz";
30 input-enable;
[all …]
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
21 input-enable;
31 drive-strength = "r0-5";
32 bias-pull-up;
33 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1021dag5a-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
27 bias-disable;
28 drive-strength = "r0-6";
29 slew-rate = "fast";
30 nxp,speed = "50-mhz";
31 input-enable;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1064dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
28 drive-strength = "r0-6";
29 bias-pull-down;
30 bias-pull-down-value = "100k";
31 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi2 * SPDX-License-Identifier: Apache-2.0
7 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
16 bias-disable;
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
26 drive-strength = "r0-6";
27 slew-rate = "fast";
28 nxp,speed = "50-mhz";
29 bias-pull-down-value = "100k";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1015_evk/
Dmimxrt1015_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1015daf5a-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
27 drive-strength = "r0-6";
28 drive-open-drain;
29 slew-rate = "slow";
30 nxp,speed = "100-mhz";
31 input-enable;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
28 drive-strength = "r0-6";
29 bias-pull-down;
30 bias-pull-down-value = "100k";
31 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1052dvl6b-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
28 drive-strength = "r0-6";
29 bias-pull-down;
30 bias-pull-down-value = "100k";
31 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/madmachine/mm_swiftio/
Dmm_swiftio-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1052dvl6b-pinctrl.dtsi>
26 drive-strength = "r0-6";
27 slew-rate = "slow";
28 nxp,speed = "100-mhz";
36 drive-strength = "r0-6";
37 drive-open-drain;
38 slew-rate = "slow";
39 nxp,speed = "100-mhz";
40 input-enable;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1010_evk/
Dmimxrt1010_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1011dae5a-pinctrl.dtsi>
17 drive-strength = "r0-4";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
26 drive-strength = "r0-4";
27 drive-open-drain;
28 slew-rate = "slow";
29 nxp,speed = "100-mhz";
30 input-enable;
[all …]
/Zephyr-latest/boards/madmachine/mm_feather/
Dmm_feather-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
16 drive-strength = "r0-6";
17 drive-open-drain;
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
20 input-enable;
28 drive-strength = "r0-6";
29 drive-open-drain;
30 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1040_evk/
Dmimxrt1040_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1042xjm5b-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
27 drive-strength = "r0-6";
28 slew-rate = "fast";
29 nxp,speed = "100-mhz";
38 drive-strength = "r0-6";
39 drive-open-drain;
[all …]
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dcy8ckit_062s2_ai.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "CY8CKIT-062S2-AI PSOC 6 AI Evaluation Kit";
18 zephyr,shell-uart = &uart5;
30 compatible = "gpio-leds";
42 compatible = "gpio-keys";
53 clock-frequency = <100000000>;
57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "cy8cproto_063_ble-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit";
19 uart-5 = &uart5;
29 zephyr,shell-uart = &uart5;
30 zephyr,bt-hci = &bluetooth;
33 /delete-node/ cpu@0;
36 compatible = "gpio-leds";
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
Dst,stm32u5-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32u5-msi-clock"
9 - name: st,stm32-msi-clock.yaml
10 property-blocklist:
11 - msi-range
15 msi-range:
22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
[all …]
Dst,stm32-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-msi-clock"
8 include: [clock-controller.yaml, base.yaml]
11 msi-range:
18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
22 - 4 # range 4 around 1M Hz
23 - 5 # range 5 around 2 MHz
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
22 slow slew rate, and 100 MHZ speed.
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
[all …]
Dnxp,s32ze-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
49 pinctrl-0 = <&uart0_default>;
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_062_4343w/
Dcy8cproto_062_4343w.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "cy8cproto_062_4343w-common.dtsi"
10 #include "cy8cproto_062_4343w-pinctrl.dtsi"
17 uart-5 = &uart5;
18 i2c-0 = &i2c3;
27 zephyr,shell-uart = &uart5;
28 zephyr,bt-hci = &bt_hci_uart;
37 compatible = "infineon,cat1-uart";
39 current-speed = <115200>;
[all …]
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
14 ext-sdram = <&sdram2>;
15 def-back-color-red = <0>;
16 def-back-color-green = <0>;
17 def-back-color-blue = <0>;
24 div-m = <5>;
25 mul-n = <132>;
26 div-p = <2>;
27 div-q = <2>;
[all …]
/Zephyr-latest/boards/intel/ish/
DKconfig.defconfig3 # SPDX-License-Identifier: Apache-2.0
13 default 2000 if APIC_TIMER_TSC # APIC timer's frequency is 19.2 MHZ or 100 MHZ
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c4 * SPDX-License-Identifier: Apache-2.0
11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
DKconfig.soc3 # SPDX-License-Identifier: Apache-2.0
6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
13 Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
14 SoC series (single core ARM Cortex-A9).
20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
21 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,

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