Lines Matching +full:100 +full:- +full:mhz
4 * SPDX-License-Identifier: Apache-2.0
11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
52 * 200 Mhz <= Fvco <= 400 Mhz
58 sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M; in arc_iot_pll_conf_reg()
60 sysconf_reg_ptr->PLLCON = val | (0x52000000); in arc_iot_pll_conf_reg()
62 sysconf_reg_ptr->PLLCON = val | (1 << PLLCON_BIT_OFFSET_PLLRST); in arc_iot_pll_conf_reg()
63 sysconf_reg_ptr->PLLCON = val & (~(1 << PLLCON_BIT_OFFSET_PLLRST)); in arc_iot_pll_conf_reg()
65 while (!(sysconf_reg_ptr->PLLSTAT & (1 << PLLSTAT_BIT_OFFSET_PLLSTB))) { in arc_iot_pll_conf_reg()
69 sysconf_reg_ptr->CLKSEL = CLKSEL_PLL; in arc_iot_pll_conf_reg()
71 sysconf_reg_ptr->AHBCLKDIV_SEL |= 1; in arc_iot_pll_conf_reg()
73 sysconf_reg_ptr->AHBCLKDIV = 0x1; in arc_iot_pll_conf_reg()
81 sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M; in arc_iot_pll_fout_config()
91 return -1; in arc_iot_pll_fout_config()
94 /* config eflash clk, must be < 100 Mhz */ in arc_iot_pll_fout_config()
95 if (freq > 100) { in arc_iot_pll_fout_config()
108 sysconf_reg_ptr->AHBCLKDIV = div; in arc_iot_ahb_clk_divisor()
117 sysconf_reg_ptr->AHBCLKEN |= (1 << dev); in arc_iot_ahb_clk_enable()
126 sysconf_reg_ptr->AHBCLKEN &= (~(1 << dev)); in arc_iot_ahb_clk_disable()
131 sysconf_reg_ptr->APBCLKDIV = div; in arc_iot_apb_clk_divisor()
140 sysconf_reg_ptr->APBCLKEN |= (1 << dev); in arc_iot_apb_clk_enable()
149 sysconf_reg_ptr->APBCLKEN &= (~(1 << dev)); in arc_iot_apb_clk_disable()
154 sysconf_reg_ptr->SDIO_REFCLK_DIV; in arc_iot_dio_clk_divisor()
160 sysconf_reg_ptr->SPI_MST_CLKDIV = in arc_iot_spi_master_clk_divisor()
161 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffffff00) | div; in arc_iot_spi_master_clk_divisor()
163 sysconf_reg_ptr->SPI_MST_CLKDIV = in arc_iot_spi_master_clk_divisor()
164 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffff00ff) | (div << 8); in arc_iot_spi_master_clk_divisor()
166 sysconf_reg_ptr->SPI_MST_CLKDIV = in arc_iot_spi_master_clk_divisor()
167 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xff00ffff) | (div << 16); in arc_iot_spi_master_clk_divisor()
174 sysconf_reg_ptr->GPIO8B_DBCLK_DIV = in arc_iot_gpio8b_dbclk_div()
175 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffffff00) | div; in arc_iot_gpio8b_dbclk_div()
177 sysconf_reg_ptr->GPIO8B_DBCLK_DIV = in arc_iot_gpio8b_dbclk_div()
178 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffff00ff) | (div << 8); in arc_iot_gpio8b_dbclk_div()
180 sysconf_reg_ptr->GPIO8B_DBCLK_DIV = in arc_iot_gpio8b_dbclk_div()
181 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xff00ffff) | (div << 16); in arc_iot_gpio8b_dbclk_div()
183 sysconf_reg_ptr->GPIO8B_DBCLK_DIV = in arc_iot_gpio8b_dbclk_div()
184 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0x00ffffff) | (div << 24); in arc_iot_gpio8b_dbclk_div()
191 sysconf_reg_ptr->GPIO4B_DBCLK_DIV = in arc_iot_gpio4b_dbclk_div()
192 (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xffffff00) | div; in arc_iot_gpio4b_dbclk_div()
194 sysconf_reg_ptr->GPIO4B_DBCLK_DIV = in arc_iot_gpio4b_dbclk_div()
195 (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xffff00ff) | (div << 8); in arc_iot_gpio4b_dbclk_div()
197 sysconf_reg_ptr->GPIO4B_DBCLK_DIV = in arc_iot_gpio4b_dbclk_div()
198 (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xff00ffff) | (div << 16); in arc_iot_gpio4b_dbclk_div()
204 sysconf_reg_ptr->I2S_TX_SCLKDIV = div; in arc_iot_i2s_tx_clk_div()
209 sysconf_reg_ptr->I2S_RX_SCLKDIV = div; in arc_iot_i2s_rx_clk_div()
214 sysconf_reg_ptr->I2S_RX_SCLKSEL = sel; in arc_iot_i2s_rx_clk_sel()
219 sysconf_reg_ptr->RSTCON = 0x55AA6699; in arc_iot_syscon_reset()
224 if (sysconf_reg_ptr->RSTSTAT & SYS_RST_SOFTWARE_ON) { in arc_iot_is_poweron_rst()
234 sysconf_reg_ptr->DVFS_CLKDIV = in arc_iot_dvfs_clk_divisor()
235 (sysconf_reg_ptr->DVFS_CLKDIV & 0xffffff00) | div; in arc_iot_dvfs_clk_divisor()
237 sysconf_reg_ptr->DVFS_CLKDIV = in arc_iot_dvfs_clk_divisor()
238 (sysconf_reg_ptr->DVFS_CLKDIV & 0xffff00ff) | (div << 8); in arc_iot_dvfs_clk_divisor()
240 sysconf_reg_ptr->DVFS_CLKDIV = in arc_iot_dvfs_clk_divisor()
241 (sysconf_reg_ptr->DVFS_CLKDIV & 0xff00ffff) | (div << 16); in arc_iot_dvfs_clk_divisor()
243 sysconf_reg_ptr->DVFS_CLKDIV = in arc_iot_dvfs_clk_divisor()
244 (sysconf_reg_ptr->DVFS_CLKDIV & 0x00ffffff) | (div << 24); in arc_iot_dvfs_clk_divisor()
253 sysconf_reg_ptr->DVFS_VDDSET = in arc_iot_dvfs_vdd_config()
254 (sysconf_reg_ptr->DVFS_VDDSET & 0xfffffff0) | val; in arc_iot_dvfs_vdd_config()
256 sysconf_reg_ptr->DVFS_VDDSET = in arc_iot_dvfs_vdd_config()
257 (sysconf_reg_ptr->DVFS_VDDSET & 0xffffff0f) | (val << 4); in arc_iot_dvfs_vdd_config()
259 sysconf_reg_ptr->DVFS_VDDSET = in arc_iot_dvfs_vdd_config()
260 (sysconf_reg_ptr->DVFS_VDDSET & 0xfffff0ff) | (val << 8); in arc_iot_dvfs_vdd_config()
262 sysconf_reg_ptr->DVFS_CLKDIV = in arc_iot_dvfs_vdd_config()
263 (sysconf_reg_ptr->DVFS_CLKDIV & 0xffff0fff) | (val << 12); in arc_iot_dvfs_vdd_config()
269 sysconf_reg_ptr->DVFS_VWTIME = time; in arc_iot_dvfs_vwtime_config()
274 sysconf_reg_ptr->PMC_PUWTIME = time; in arc_iot_pmc_pwwtime_config()
279 sysconf_reg_ptr->UART3SCLK_DIV = div; in arc_iot_uart3_clk_divisor()
284 sysconf_reg_ptr->RESET_PD_VECTOR = addr; in arc_iot_reset_powerdown_vector()
289 uint32_t val = sysconf_reg_ptr->TIMER_PAUSE; in arc_iot_pwm_timer_pause()
301 sysconf_reg_ptr->TIMER_PAUSE = val; in arc_iot_pwm_timer_pause()
306 sysconf_reg_ptr->AHBCLKDIV |= (div << 8); in arc_iot_eflash_clk_div()