1# Copyright (c) 2020 Nuvoton Technology Corporation.
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Nuvoton, NPCX PCC (Power and Clock Controller) node.
6  Besides power management, this node is also in charge of configuring the
7  Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8  High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
9  and most of NPCX hardware modules.
10
11  Here is an example of configuring OFMCLK and the other clock sources derived
12  from it in board dts file.
13  &pcc {
14      clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15      core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16      apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17      apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18      apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
19  };
20
21compatible: "nuvoton,npcx-pcc"
22
23include: [clock-controller.yaml, base.yaml]
24
25properties:
26  reg:
27    required: true
28
29  clock-frequency:
30    required: true
31    type: int
32    description: |
33      Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
34      only the following values are allowed:
35        120000000, 120 MHz
36        100000000, 100 MHz
37        96000000, 96 MHz
38        90000000, 90 MHz
39        80000000, 80 MHz
40        66000000, 66 MHz
41        50000000, 50 MHz
42        48000000, 48 MHz
43    enum:
44      - 120000000
45      - 100000000
46      - 96000000
47      - 90000000
48      - 80000000
49      - 66000000
50      - 50000000
51      - 48000000
52
53  core-prescaler:
54    type: int
55    required: true
56    description: |
57      Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
58      dividing OFMCLK(MCLK) and needs to meet the following requirements.
59      - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
60      = Only the following values are allowed:
61        1, CORE_CLK = OFMCLK
62        2, CORE_CLK = OFMCLK / 2
63        3, CORE_CLK = OFMCLK / 3
64        4, CORE_CLK = OFMCLK / 4
65        5, CORE_CLK = OFMCLK / 5
66        6, CORE_CLK = OFMCLK / 6
67        7, CORE_CLK = OFMCLK / 7
68        8, CORE_CLK = OFMCLK / 8
69        9, CORE_CLK = OFMCLK / 9
70        10, CORE_CLK = OFMCLK / 10
71    enum:
72      - 1
73      - 2
74      - 3
75      - 4
76      - 5
77      - 6
78      - 7
79      - 8
80      - 9
81      - 10
82
83  apb1-prescaler:
84    type: int
85    required: true
86    description: |
87      APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
88      OFMCLK(MCLK) and needs to meet the following requirements.
89      - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
90      - APB1_CLK must be an integer division (including 1) of CORE_CLK.
91      = Only the following values are allowed:
92        1, APB1_CLK = OFMCLK
93        2, APB1_CLK = OFMCLK / 2
94        3, APB1_CLK = OFMCLK / 3
95        4, APB1_CLK = OFMCLK / 4
96        5, APB1_CLK = OFMCLK / 5
97        6, APB1_CLK = OFMCLK / 6
98        7, APB1_CLK = OFMCLK / 7
99        8, APB1_CLK = OFMCLK / 8
100        9, APB1_CLK = OFMCLK / 9
101        10, APB1_CLK = OFMCLK / 10
102    enum:
103      - 1
104      - 2
105      - 3
106      - 4
107      - 5
108      - 6
109      - 7
110      - 8
111      - 9
112      - 10
113
114  apb2-prescaler:
115    type: int
116    required: true
117    description: |
118      APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
119      OFMCLK(MCLK) and needs to meet the following requirements.
120      - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
121      - APB2_CLK must be an integer division (including 1) of CORE_CLK.
122      = Only the following values are allowed:
123        1, APB2_CLK = OFMCLK
124        2, APB2_CLK = OFMCLK / 2
125        3, APB2_CLK = OFMCLK / 3
126        4, APB2_CLK = OFMCLK / 4
127        5, APB2_CLK = OFMCLK / 5
128        6, APB2_CLK = OFMCLK / 6
129        7, APB2_CLK = OFMCLK / 7
130        8, APB2_CLK = OFMCLK / 8
131        9, APB2_CLK = OFMCLK / 9
132        10, APB2_CLK = OFMCLK / 10
133    enum:
134      - 1
135      - 2
136      - 3
137      - 4
138      - 5
139      - 6
140      - 7
141      - 8
142      - 9
143      - 10
144
145  apb3-prescaler:
146    type: int
147    required: true
148    description: |
149      APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
150      OFMCLK(MCLK) and needs to meet the following requirements.
151      - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
152      - APB3_CLK must be an integer division (including 1) of CORE_CLK.
153      = Only the following values are allowed:
154        1, APB3_CLK = OFMCLK
155        2, APB3_CLK = OFMCLK / 2
156        3, APB3_CLK = OFMCLK / 3
157        4, APB3_CLK = OFMCLK / 4
158        5, APB3_CLK = OFMCLK / 5
159        6, APB3_CLK = OFMCLK / 6
160        7, APB3_CLK = OFMCLK / 7
161        8, APB3_CLK = OFMCLK / 8
162        9, APB3_CLK = OFMCLK / 9
163        10, APB3_CLK = OFMCLK / 10
164    enum:
165      - 1
166      - 2
167      - 3
168      - 4
169      - 5
170      - 6
171      - 7
172      - 8
173      - 9
174      - 10
175
176  apb4-prescaler:
177    type: int
178    description: |
179      APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
180      OFMCLK(MCLK) and needs to meet the following requirements.
181      - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
182      - APB4_CLK must be an integer division (including 1) of CORE_CLK.
183      = Only the following values are allowed:
184        1, APB4_CLK = OFMCLK
185        2, APB4_CLK = OFMCLK / 2
186        3, APB4_CLK = OFMCLK / 3
187        4, APB4_CLK = OFMCLK / 4
188        5, APB4_CLK = OFMCLK / 5
189        6, APB4_CLK = OFMCLK / 6
190        7, APB4_CLK = OFMCLK / 7
191        8, APB4_CLK = OFMCLK / 8
192        9, APB4_CLK = OFMCLK / 9
193        10, APB4_CLK = OFMCLK / 10
194    enum:
195      - 1
196      - 2
197      - 3
198      - 4
199      - 5
200      - 6
201      - 7
202      - 8
203      - 9
204      - 10
205
206  ram-pd-depth:
207    type: int
208    enum:
209      - 8
210      - 12
211      - 15
212    description: |
213      Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
214      Each bit in RAM_PDn can power down the relevant RAM block by setting
215      itself to 1 for better power consumption and this valid bit-depth
216      varies in different NPCX series.
217
218  pwdwn-ctl-val:
219    type: array
220    required: true
221    description: |
222      Power-down (turn off clock) the modules during system initialization for
223      better power consumption.
224
225clock-cells:
226  - bus
227  - ctl
228  - bit
229