1#
2# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
3# SPDX-License-Identifier: Apache-2.0
4#
5# Device data: comp.
6# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
7#
8
9config SOC_SERIES_XC7ZXXXS
10	bool
11	select SOC_FAMILY_XILINX_ZYNQ7000
12	help
13	  Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
14	  SoC series (single core ARM Cortex-A9).
15
16config SOC_XILINX_XC7Z007S
17	bool
18	select SOC_SERIES_XC7ZXXXS
19	help
20	  1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
21	  23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
22
23config SOC_XILINX_XC7Z012S
24	bool
25	select SOC_SERIES_XC7ZXXXS
26	help
27	  1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
28	  55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
29	  up to 4 transceivers.
30
31config SOC_XILINX_XC7Z014S
32	bool
33	select SOC_SERIES_XC7ZXXXS
34	help
35	  1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
36	  65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
37
38config SOC_SERIES
39	default "xc7zxxxs" if SOC_SERIES_XC7ZXXXS
40
41config SOC
42	default "xc7z007s" if SOC_XILINX_XC7Z007S
43	default "xc7z012s" if SOC_XILINX_XC7Z012S
44	default "xc7z014s" if SOC_XILINX_XC7Z014S
45