1/*
2 * Copyright (c) 2022, NXP
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Note: File generated by gen_board_pinctrl.py
6 * from mimxrt1060_evk.mex
7 */
8
9#include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
10
11&pinctrl {
12	/* ADC1 inputs 0 and 15 */
13	pinmux_adc1: pinmux_adc1 {
14		group0 {
15			pinmux = <&iomuxc_gpio_ad_b1_11_adc1_in0>,
16				<&iomuxc_gpio_ad_b1_10_adc1_in15>;
17			bias-disable;
18			drive-strength = "r0-6";
19			slew-rate = "slow";
20			nxp,speed = "100-mhz";
21		};
22	};
23
24	/* conflicts with lpuart3 */
25	pinmux_csi: pinmux_csi {
26		group0 {
27			pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>;
28			drive-strength = "r0-6";
29			bias-pull-down;
30			bias-pull-down-value = "100k";
31			slew-rate = "slow";
32			nxp,speed = "100-mhz";
33		};
34		group1 {
35			pinmux = <&iomuxc_gpio_ad_b1_04_csi_pixclk>,
36				<&iomuxc_gpio_ad_b1_05_csi_mclk>,
37				<&iomuxc_gpio_ad_b1_06_csi_vsync>,
38				<&iomuxc_gpio_ad_b1_07_csi_hsync>,
39				<&iomuxc_gpio_ad_b1_08_csi_data09>,
40				<&iomuxc_gpio_ad_b1_09_csi_data08>,
41				<&iomuxc_gpio_ad_b1_10_csi_data07>,
42				<&iomuxc_gpio_ad_b1_11_csi_data06>,
43				<&iomuxc_gpio_ad_b1_12_csi_data05>,
44				<&iomuxc_gpio_ad_b1_13_csi_data04>,
45				<&iomuxc_gpio_ad_b1_14_csi_data03>,
46				<&iomuxc_gpio_ad_b1_15_csi_data02>;
47			drive-strength = "r0-6";
48			slew-rate = "slow";
49			nxp,speed = "100-mhz";
50		};
51	};
52
53	pinmux_enet: pinmux_enet {
54		group0 {
55			pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>;
56			bias-disable;
57			drive-strength = "r0-6";
58			slew-rate = "fast";
59			nxp,speed = "50-mhz";
60			input-enable;
61		};
62		group1 {
63			pinmux = <&iomuxc_gpio_b1_04_enet_rx_data0>,
64				<&iomuxc_gpio_b1_05_enet_rx_data1>,
65				<&iomuxc_gpio_b1_06_enet_rx_en>,
66				<&iomuxc_gpio_b1_07_enet_tx_data0>,
67				<&iomuxc_gpio_b1_08_enet_tx_data1>,
68				<&iomuxc_gpio_b1_09_enet_tx_en>,
69				<&iomuxc_gpio_b1_11_enet_rx_er>;
70			drive-strength = "r0-5";
71			bias-pull-up;
72			bias-pull-up-value = "100k";
73			slew-rate = "fast";
74			nxp,speed = "200-mhz";
75		};
76	};
77
78	pinmux_enet_mdio: pinmux_enet_mdio {
79		group0 {
80			pinmux = <&iomuxc_gpio_emc_40_enet_mdc>,
81				<&iomuxc_gpio_emc_41_enet_mdio>,
82				<&iomuxc_gpio_ad_b0_10_gpio1_io10>,
83				<&iomuxc_gpio_ad_b0_09_gpio1_io09>;
84			drive-strength = "r0-5";
85			bias-pull-up;
86			bias-pull-up-value = "100k";
87			slew-rate = "fast";
88			nxp,speed = "200-mhz";
89		};
90	};
91
92	pinmux_ptp: pinmux_ptp {
93		group0 {
94			pinmux = <&iomuxc_gpio_ad_b1_02_enet_1588_event2_out>,
95				<&iomuxc_gpio_ad_b1_03_enet_1588_event2_in>;
96			drive-strength = "r0-6";
97			slew-rate = "slow";
98			nxp,speed = "100-mhz";
99		};
100	};
101
102
103	pinmux_flexcan3: pinmux_flexcan3 {
104		group0 {
105			pinmux = <&iomuxc_gpio_ad_b0_14_flexcan3_tx>,
106				<&iomuxc_gpio_ad_b0_15_flexcan3_rx>;
107			drive-strength = "r0-6";
108			slew-rate = "slow";
109			nxp,speed = "100-mhz";
110		};
111	};
112
113	/* flexpwm output for board LED */
114	pinmux_flexpwm2_3: pinmux_flexpwm2_3 {
115		group0 {
116			pinmux = <&iomuxc_gpio_ad_b0_09_flexpwm2_pwma3>;
117			drive-strength = "r0-4";
118			bias-pull-up;
119			bias-pull-up-value = "47k";
120			slew-rate = "slow";
121			nxp,speed = "100-mhz";
122		};
123	};
124
125	/* Conflicts with SD and SPI pins. Requires R281/R356 be populated */
126	pinmux_flexpwm1_0: pinmux_flexpwm1_0 {
127		group0 {
128			pinmux = <&iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0>;
129			drive-strength = "r0-4";
130			bias-pull-up;
131			bias-pull-up-value = "47k";
132			slew-rate = "slow";
133			nxp,speed = "100-mhz";
134		};
135	};
136
137	pinmux_flexpwm1: pinmux_flexpwm1 {
138		group0 {
139			pinmux = <&iomuxc_gpio_ad_b0_10_flexpwm1_pwma3>;
140			drive-strength = "r0-4";
141			bias-pull-up;
142			bias-pull-up-value = "47k";
143			slew-rate = "slow";
144			nxp,speed = "100-mhz";
145		};
146	};
147
148	pinmux_flexspi1: pinmux_flexspi1 {
149		group0 {
150			pinmux = <&iomuxc_gpio_sd_b1_05_flexspi_a_dqs>;
151			drive-strength = "r0-6";
152			input-schmitt-enable;
153			bias-pull-down;
154			bias-pull-down-value = "100k";
155			slew-rate = "fast";
156			nxp,speed = "200-mhz";
157			input-enable;
158		};
159		group1 {
160			pinmux = <&iomuxc_gpio_sd_b1_03_flexspi_b_data0>,
161				<&iomuxc_gpio_sd_b1_00_flexspi_b_data3>,
162				<&iomuxc_gpio_sd_b1_01_flexspi_b_data2>,
163				<&iomuxc_gpio_sd_b1_02_flexspi_b_data1>,
164				<&iomuxc_gpio_sd_b1_04_flexspi_b_sclk>,
165				<&iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b>,
166				<&iomuxc_gpio_sd_b1_07_flexspi_a_sclk>,
167				<&iomuxc_gpio_sd_b1_08_flexspi_a_data0>,
168				<&iomuxc_gpio_sd_b1_09_flexspi_a_data1>,
169				<&iomuxc_gpio_sd_b1_10_flexspi_a_data2>,
170				<&iomuxc_gpio_sd_b1_11_flexspi_a_data3>;
171			drive-strength = "r0-6";
172			slew-rate = "fast";
173			nxp,speed = "200-mhz";
174			input-enable;
175		};
176	};
177
178	/* Configures pin routing and optionally pin electrical features. */
179	pinmux_lcdif: pinmux_lcdif {
180		group0 {
181			pinmux = <&iomuxc_gpio_b0_00_lcdif_clk>,
182				<&iomuxc_gpio_b0_01_lcdif_enable>,
183				<&iomuxc_gpio_b0_02_lcdif_hsync>,
184				<&iomuxc_gpio_b0_03_lcdif_vsync>,
185				<&iomuxc_gpio_b0_04_lcdif_data00>,
186				<&iomuxc_gpio_b0_05_lcdif_data01>,
187				<&iomuxc_gpio_b0_06_lcdif_data02>,
188				<&iomuxc_gpio_b0_07_lcdif_data03>,
189				<&iomuxc_gpio_b0_08_lcdif_data04>,
190				<&iomuxc_gpio_b0_09_lcdif_data05>,
191				<&iomuxc_gpio_b0_10_lcdif_data06>,
192				<&iomuxc_gpio_b0_11_lcdif_data07>,
193				<&iomuxc_gpio_b0_12_lcdif_data08>,
194				<&iomuxc_gpio_b0_13_lcdif_data09>,
195				<&iomuxc_gpio_b0_14_lcdif_data10>,
196				<&iomuxc_gpio_b0_15_lcdif_data11>,
197				<&iomuxc_gpio_b1_00_lcdif_data12>,
198				<&iomuxc_gpio_b1_01_lcdif_data13>,
199				<&iomuxc_gpio_b1_02_lcdif_data14>,
200				<&iomuxc_gpio_b1_03_lcdif_data15>;
201			drive-strength = "r0-6";
202			input-schmitt-enable;
203			bias-pull-up;
204			bias-pull-up-value = "100k";
205			slew-rate = "slow";
206			nxp,speed = "100-mhz";
207		};
208		group1 {
209			pinmux = <&iomuxc_gpio_ad_b0_02_gpio1_io02>,
210				<&iomuxc_gpio_b1_15_gpio2_io31>;
211			drive-strength = "r0-6";
212			slew-rate = "slow";
213			nxp,speed = "100-mhz";
214		};
215	};
216
217	pinmux_lpi2c1: pinmux_lpi2c1 {
218		group0 {
219			pinmux = <&iomuxc_gpio_ad_b1_01_lpi2c1_sda>,
220				<&iomuxc_gpio_ad_b1_00_lpi2c1_scl>;
221			drive-strength = "r0-6";
222			drive-open-drain;
223			slew-rate = "slow";
224			nxp,speed = "100-mhz";
225			input-enable;
226		};
227	};
228
229	/* Conflicts with USDHC pins. Connect R278, R279, R280, and R281 on evk board */
230	pinmux_lpspi1: pinmux_lpspi1 {
231		group0 {
232			pinmux = <&iomuxc_gpio_sd_b0_01_lpspi1_pcs0>,
233				<&iomuxc_gpio_sd_b0_00_lpspi1_sck>,
234				<&iomuxc_gpio_sd_b0_03_lpspi1_sdi>,
235				<&iomuxc_gpio_sd_b0_02_lpspi1_sdo>;
236			drive-strength = "r0-6";
237			slew-rate = "slow";
238			nxp,speed = "100-mhz";
239		};
240	};
241
242	/* conflicts with lcdif pins */
243	pinmux_lpspi3: pinmux_lpspi3 {
244		group0 {
245			pinmux = <&iomuxc_gpio_ad_b0_03_lpspi3_pcs0>,
246				<&iomuxc_gpio_ad_b0_00_lpspi3_sck>,
247				<&iomuxc_gpio_ad_b0_02_lpspi3_sdi>,
248				<&iomuxc_gpio_ad_b0_01_lpspi3_sdo>;
249			drive-strength = "r0-6";
250			slew-rate = "slow";
251			nxp,speed = "100-mhz";
252		};
253	};
254
255	pinmux_lpuart1: pinmux_lpuart1 {
256		group0 {
257			pinmux = <&iomuxc_gpio_ad_b0_13_lpuart1_rx>,
258				<&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
259			drive-strength = "r0-6";
260			slew-rate = "slow";
261			nxp,speed = "100-mhz";
262		};
263	};
264
265	pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
266		group0 {
267			pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
268			drive-strength = "r0";
269			bias-pull-up;
270			bias-pull-up-value = "100k";
271			slew-rate = "slow";
272			nxp,speed = "50-mhz";
273		};
274		group1 {
275			pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
276			drive-strength = "r0-6";
277			slew-rate = "slow";
278			nxp,speed = "100-mhz";
279		};
280	};
281
282	pinmux_lpuart3: pinmux_lpuart3 {
283		group0 {
284			pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
285				<&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
286			drive-strength = "r0-6";
287			slew-rate = "slow";
288			nxp,speed = "100-mhz";
289		};
290	};
291
292	/* Flow control for lpuart3 */
293	pinmux_lpuart3_flow_control: pinmux_lpuart3_flow_control {
294		group0 {
295			pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
296				<&iomuxc_gpio_ad_b1_07_lpuart3_rx>,
297				<&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>,
298				<&iomuxc_gpio_ad_b1_05_lpuart3_rts_b>;
299			drive-strength = "r0-6";
300			slew-rate = "slow";
301			nxp,speed = "100-mhz";
302		};
303	};
304
305	pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
306		group0 {
307			pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>;
308			drive-strength = "r0";
309			bias-pull-up;
310			bias-pull-up-value = "100k";
311			slew-rate = "slow";
312			nxp,speed = "100-mhz";
313		};
314		group1 {
315			pinmux = <&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
316			drive-strength = "r0-6";
317			slew-rate = "slow";
318			nxp,speed = "100-mhz";
319		};
320	};
321
322	pinmux_sai1: pinmux_sai1 {
323		group0 {
324			pinmux = <&iomuxc_gpio_ad_b1_09_sai1_mclk>,
325				<&iomuxc_gpio_ad_b1_13_sai1_tx_data0>,
326				<&iomuxc_gpio_ad_b1_12_sai1_rx_data0>,
327				<&iomuxc_gpio_ad_b1_14_sai1_tx_bclk>,
328				<&iomuxc_gpio_ad_b1_15_sai1_tx_sync>;
329			drive-strength = "r0-6";
330			slew-rate = "slow";
331			nxp,speed = "100-mhz";
332		};
333	};
334
335	/* Note SWO is configured with a cpu frequency of 132MHz and SWO frequency of 7500KHz */
336	pinmux_swo: pinmux_swo {
337		group0 {
338			pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>;
339			bias-disable;
340			drive-strength = "r0-7";
341			slew-rate = "fast";
342			nxp,speed = "200-mhz";
343		};
344	};
345
346	pinmux_usdhc1: pinmux_usdhc1 {
347		group0 {
348			pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
349			bias-disable;
350			drive-strength = "r0";
351			input-schmitt-enable;
352			slew-rate = "fast";
353			nxp,speed = "100-mhz";
354		};
355		group1 {
356			pinmux = <&iomuxc_gpio_b1_12_gpio2_io28>,
357				<&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
358				<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
359				<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
360				<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
361				<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
362			drive-strength = "r0";
363			input-schmitt-enable;
364			bias-pull-up;
365			bias-pull-up-value = "47k";
366			slew-rate = "fast";
367			nxp,speed = "100-mhz";
368		};
369		group2 {
370			pinmux = <&iomuxc_gpio_b1_14_usdhc1_vselect>;
371			drive-strength = "r0-4";
372			input-schmitt-enable;
373			bias-pull-up;
374			bias-pull-up-value = "47k";
375			slew-rate = "fast";
376			nxp,speed = "100-mhz";
377		};
378		group3 {
379			pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>;
380			drive-strength = "r0-6";
381			slew-rate = "slow";
382			nxp,speed = "100-mhz";
383		};
384	};
385
386	/* fast pinmux settings for USDHC (over 100 Mhz) */
387	pinmux_usdhc1_fast: pinmux_usdhc1_fast {
388		group0 {
389			pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
390			bias-disable;
391			drive-strength = "r0-7";
392			input-schmitt-enable;
393			slew-rate = "fast";
394			nxp,speed = "200-mhz";
395		};
396		group1 {
397			pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
398				<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
399				<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
400				<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
401				<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
402			drive-strength = "r0-7";
403			input-schmitt-enable;
404			bias-pull-up;
405			bias-pull-up-value = "47k";
406			slew-rate = "fast";
407			nxp,speed = "200-mhz";
408		};
409	};
410
411	/* medium pinmux settings for USDHC (under 100 Mhz) */
412	pinmux_usdhc1_med: pinmux_usdhc1_med {
413		group0 {
414			pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
415			bias-disable;
416			drive-strength = "r0-7";
417			input-schmitt-enable;
418			slew-rate = "fast";
419			nxp,speed = "100-mhz";
420		};
421		group1 {
422			pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
423				<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
424				<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
425				<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
426				<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
427			drive-strength = "r0-7";
428			input-schmitt-enable;
429			bias-pull-up;
430			bias-pull-up-value = "47k";
431			slew-rate = "fast";
432			nxp,speed = "100-mhz";
433		};
434	};
435
436	/* slow pinmux settings for USDHC (under 50 Mhz) */
437	pinmux_usdhc1_slow: pinmux_usdhc1_slow {
438		group0 {
439			pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
440			bias-disable;
441			drive-strength = "r0-7";
442			input-schmitt-enable;
443			slew-rate = "fast";
444			nxp,speed = "50-mhz";
445		};
446		group1 {
447			pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
448				<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
449				<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
450				<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
451				<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
452			drive-strength = "r0-7";
453			input-schmitt-enable;
454			bias-pull-up;
455			bias-pull-up-value = "47k";
456			slew-rate = "fast";
457			nxp,speed = "50-mhz";
458		};
459	};
460};
461