1# Copyright 2022, 2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  NXP S32 pinctrl node for S32Z/E SoCs.
6
7  The NXP S32 pin controller is a singleton node responsible for controlling
8  the pin function selection and pin properties. This node, labeled 'pinctrl' in
9  the SoC's devicetree, will define pin configurations in pin groups. Each group
10  within the pin configuration defines the pin configuration for a peripheral,
11  and each numbered subgroup in the pin group defines all the pins for that
12  peripheral with the same configuration properties. The 'pinmux' property in
13  a group selects the pins to be configured, and the remaining properties set
14  configuration values for those pins.
15
16  For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
17  board or application devicetree overlay as follows:
18
19    /* Include the SoC package header containing the predefined pins definitions */
20    #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
21
22    &pinctrl {
23      uart0_default: uart0_default {
24        group1 {
25          pinmux = <PB10_LIN_0_TX>;
26          output-enable;
27        };
28        group2 {
29          pinmux = <PB11_LIN_0_RX>;
30          input-enable;
31        };
32      };
33    };
34
35  The 'uart0_default' node contains the pin configurations for a particular state
36  of a device. The 'default' state is the active state. Other states for the same
37  device can be specified in separate child nodes of 'pinctrl'.
38
39  In addition to 'pinmux' property, each group can contain other properties such as
40  'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41  'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42  output buffer use 'output-enable'.
43
44  To link the pin configurations with UART0 device, use pinctrl-N property in the
45  device node, where 'N' is the zero-based state index (0 is the default state).
46  Following previous example:
47
48    &uart0 {
49      pinctrl-0 = <&uart0_default>;
50      pinctrl-names = "default";
51      status = "okay";
52    };
53
54  If only the required properties are supplied, the pin configuration register
55  will be assigned the following reset values:
56    - input and output buffers disabled
57    - internal pull not enabled
58    - open drain disabled
59    - slew rate 4 (see description in property below).
60    - termination resistor disabled (affect LVDS pads only).
61    - current reference control disabled (affect LVDS pads only).
62    - Rx current boost disabled  (affect LVDS pads only).
63
64  Additionally:
65  - Safe Mode is always kept as reset value (disabled).
66  - Receiver Select is always kept as reset value (enables the differential vref based receiver).
67
68compatible: "nxp,s32ze-pinctrl"
69
70include: base.yaml
71
72child-binding:
73  description: NXP S32 pin controller pin group.
74  child-binding:
75    description: NXP S32 pin controller pin configuration node.
76
77    include:
78      - name: pincfg-node.yaml
79        property-allowlist:
80          - bias-pull-down
81          - bias-pull-up
82          - drive-open-drain
83          - slew-rate
84          - input-enable
85          - output-enable
86
87    properties:
88      pinmux:
89        required: true
90        type: array
91        description: |
92          An array of pins sharing the same group properties. The pins must be
93          defined using the macros from the SoC package header. These macros
94          encode all the pin muxing information in a 32-bit value.
95
96      slew-rate:
97        enum: [0, 4, 5, 6, 7]
98        default: 4
99        description: |
100          Slew rate control. Reset value is 4.
101          - For 3.3 V / 1.8 V FAST pads:
102            0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
103            4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
104            5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
105            6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
106            7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
107          - For 1.8 V GPIO pads:
108            0: FMAX_18 = 208 MHz
109            4: FMAX_18 = 150 MHz
110            5: FMAX_18 = 133 MHz
111            6: FMAX_18 = 100 MHz
112            7: FMAX_18 = 50 MHz
113          - For 3.3 V GPIO pads:
114            0: Reserved
115            4: FMAX_33 = 50 MHz
116            5: FMAX_33 = 50 MHz
117            6: FMAX_33 = 50 MHz
118            7: FMAX_33 = 1 MHz
119
120      nxp,current-reference-control:
121        type: boolean
122        description: |
123          This configuration applies the current reference control to
124          the associated pin. It is only applicable to LVDS pads and
125          has no effect on other types of pads
126
127      nxp,termination-resistor:
128        type: boolean
129        description: |
130          This configuration applies the termination resistor to
131          the associated pin. It is only applicable to LVDS pads and
132          has no effect on other types of pads
133
134      nxp,rx-current-boost:
135        type: boolean
136        description: |
137          RX LVDS Current Boost
138          Boosts RX IO current. It is only applicable to LVDS pads and
139          has no effect on other types of pads
140          0: Current reference is 200 μA; supports data rate up to 320 Mbaud
141          1: Current reference is 1 mA; supports data rate up to 420 Mbaud
142