# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0

description: |
  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
  nodes can be autogenerated using the MCUXpresso config tools combined with
  the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
  fields in a group select the pins to be configured, and the remaining
  devicetree properties set configuration values for those pins
  for example, here is an group configuring LPUART1 pins:

  group0 {
    pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx,
      &iomuxc_gpio_ad_b0_13_lpuart1_rx>;
    drive-strength = "r0-6";
    slew-rate = "slow";
    nxp,speed = "100-mhz";
  };

  This will select GPIO_AD_B0_12 as LPUART1 TX, and GPIO_AD_B0_13 as LPUART1 RX.
  Both pins will be configured with a weak latch, drive strength of "r0-6",
  slow slew rate, and 100 MHZ speed.
  Note that the soc level iomuxc dts file can be examined to find the possible
  pinmux options. Here are the affects of each property on the
  IOMUXC SW_PAD_CTL register:
  input-schmitt-enable: HYS=1
  drive-open-drain: ODE=1
  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
  bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
  bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
  bias-disable: PKE=0
  slew-rate: SRE=<enum_idx>
  drive-strength: DSE=<enum_idx>
  nxp,speed: SPEED=<enum_idx>

  If only required properties are supplied, the pin will have the following
  configuration:
  HYS=0,
  ODE=0,
  SION=0,
  PUE=0,
  PUS=0,
  PKE=1,
  SRE=<slew-rate>,
  DSE=<drive-strength>,
  SPEED=<nxp,speed>


compatible: "nxp,mcux-rt-pinctrl"

include: base.yaml

child-binding:
  description: MCUX RT pin controller pin group
  child-binding:
    description: |
      MCUX RT pin controller pin configuration node.

    include:
      - name: pincfg-node.yaml
        property-allowlist:
          - input-schmitt-enable
          - drive-open-drain
          - input-enable
          - bias-disable
          - bias-pull-down
          - bias-pull-up

    properties:
      pinmux:
        required: true
        type: phandles
        description: |
          Pin mux selections for this group. See the soc level iomuxc DTSI file
          for a defined list of these options.
      drive-strength:
        required: true
        type: string
        enum:
          - "disabled"
          - "r0"
          - "r0-2"
          - "r0-3"
          - "r0-4"
          - "r0-5"
          - "r0-6"
          - "r0-7"
        description: |
          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
          the drive strength is expressed as a output impedance at a given voltage,
          but maximum current values can be calculated from these impedances
          for a specific load impedance.
          000 DSE_0_output_driver_disabled_ — output driver disabled
          001 DSE_1_R0_1 — 157 Ohm impedance @3.3V, 260 Ohm impedance @1.8V
          010 DSE_2_R0_2 — 78 Ohm @3.3V, 130 Ohm @1.8V
          011 DSE_3_R0_3 — 53 Ohm @3.3V, 88 Ohm @1.8V
          100 DSE_4_R0_4 — 39 Ohm @3.3V, 65 Ohm @1.8V
          101 DSE_5_R0_5 — 32 Ohm @3.3V, 52 Ohm @1.8V
          110 DSE_6_R0_6 — 32 Ohm @3.3V, 43 Ohm @1.8V
          111 DSE_7_R0_7 — 26 Ohm @3.3V, 37 Ohm @1.8V
      bias-pull-up-value:
        type: string
        default: "47k"
        enum:
          - "unused"
          - "47k"
          - "100k"
          - "22k"
        description: |
          Select the value of the pull up resistor present on this pin
          Corresponds to the PUS field in the IOMUXC peripheral.
          47k resistor selected as default due to this being the default pullup
          value on most SOC pins
          00 Unused- no change will be applied to pin
          01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
          10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
          11 PUS_2_22K_Ohm_Pull_Up — 22K Ohm Pull Up

      bias-pull-down-value:
        type: string
        default: "100k"
        enum:
          - "100k"
        description: |
          Select the value of the pull up resistor present on this pin
          Corresponds to the PUS field in the IOMUXC peripheral. 100k is
          currently the only supported pull down resistance.
          00 PUS_0_100K_Ohm_Pull_Down - 100K Ohm Pull Down
      slew-rate:
        required: true
        type: string
        enum:
          - "slow"
          - "fast"
        description: |
          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
          0 SRE_0_Slow_Slew_Rate — Slow Slew Rate
          1 SRE_1_Fast_Slew_Rate — Fast Slew Rate
      nxp,speed:
        type: string
        enum:
          - "50-mhz"
          - "100-mhz"
          - "150-mhz"
          - "200-mhz"
        description: |
          Sets pin speed. Corresponds to SPEED field in IOMUXC peripheral
          00 SPEED_0_low_50MHz_ — low(50MHz)
          01 SPEED_1_medium_100MHz_ — medium(100MHz)
          10 SPEED_2_medium_150MHz_ — medium(150MHz)
          11 SPEED_3_max_200MHz_ — max(200MHz)
