Home
last modified time | relevance | path

Searched refs:rctl (Results 26 – 50 of 114) sorted by relevance

12345

/Zephyr-latest/dts/arm/st/l0/
Dstm32l051.dtsi39 resets = <&rctl STM32_RESET(APB2, 14U)>;
48 resets = <&rctl STM32_RESET(APB2, 5U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
/Zephyr-latest/dts/arm/st/f0/
Dstm32f071.dtsi48 resets = <&rctl STM32_RESET(APB1, 18U)>;
57 resets = <&rctl STM32_RESET(APB1, 19U)>;
66 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f030X8.dtsi25 resets = <&rctl STM32_RESET(APB1, 17U)>;
56 resets = <&rctl STM32_RESET(APB1, 4U)>;
67 resets = <&rctl STM32_RESET(APB2, 16U)>;
Dstm32f051.dtsi17 resets = <&rctl STM32_RESET(APB1, 17U)>;
48 resets = <&rctl STM32_RESET(APB1, 4U)>;
59 resets = <&rctl STM32_RESET(APB2, 16U)>;
Dstm32f070.dtsi17 resets = <&rctl STM32_RESET(APB1, 17U)>;
26 resets = <&rctl STM32_RESET(APB2, 16U)>;
/Zephyr-latest/dts/arm/st/g0/
Dstm32g031.dtsi18 resets = <&rctl STM32_RESET(APB1L, 20U)>;
27 resets = <&rctl STM32_RESET(APB1L, 0U)>;
Dstm32g050.dtsi17 resets = <&rctl STM32_RESET(APB1L, 4U)>;
28 resets = <&rctl STM32_RESET(APB1L, 5U)>;
Dstm32g071.dtsi19 resets = <&rctl STM32_RESET(APB1L, 18U)>;
28 resets = <&rctl STM32_RESET(APB1L, 19U)>;
Dstm32g0b1.dtsi61 resets = <&rctl STM32_RESET(APB1L, 8U)>;
70 resets = <&rctl STM32_RESET(APB1L, 9U)>;
79 resets = <&rctl STM32_RESET(APB1L, 7U)>;
88 resets = <&rctl STM32_RESET(APB1L, 2U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4p5.dtsi101 resets = <&rctl STM32_RESET(APB1L, 18U)>;
110 resets = <&rctl STM32_RESET(APB1L, 19U)>;
119 resets = <&rctl STM32_RESET(APB1L, 20U)>;
172 resets = <&rctl STM32_RESET(APB1L, 1U)>;
194 resets = <&rctl STM32_RESET(APB1L, 2U)>;
216 resets = <&rctl STM32_RESET(APB1L, 3U)>;
238 resets = <&rctl STM32_RESET(APB1L, 5U)>;
260 resets = <&rctl STM32_RESET(APB2, 13U)>;
277 resets = <&rctl STM32_RESET(APB2, 18U)>;
343 resets = <&rctl STM32_RESET(AHB2, 22U)>;
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f105.dtsi68 resets = <&rctl STM32_RESET(APB1, 19U)>;
77 resets = <&rctl STM32_RESET(APB1, 20U)>;
106 resets = <&rctl STM32_RESET(APB1, 3U)>;
123 resets = <&rctl STM32_RESET(APB1, 4U)>;
134 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f1.dtsi107 rctl: reset-controller { label
108 compatible = "st,stm32-rcc-rctl";
179 resets = <&rctl STM32_RESET(APB2, 14U)>;
188 resets = <&rctl STM32_RESET(APB1, 17U)>;
197 resets = <&rctl STM32_RESET(APB1, 18U)>;
254 resets = <&rctl STM32_RESET(APB2, 11U)>;
271 resets = <&rctl STM32_RESET(APB1, 0U)>;
293 resets = <&rctl STM32_RESET(APB1, 1U)>;
315 resets = <&rctl STM32_RESET(APB1, 2U)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi140 rctl: reset-controller { label
141 compatible = "st,stm32-rcc-rctl";
258 resets = <&rctl STM32_RESET(APB2, 4U)>;
267 resets = <&rctl STM32_RESET(APB1, 17U)>;
276 resets = <&rctl STM32_RESET(APB1, 18U)>;
285 resets = <&rctl STM32_RESET(APB1, 19U)>;
294 resets = <&rctl STM32_RESET(APB1, 20U)>;
303 resets = <&rctl STM32_RESET(APB2, 5U)>;
312 resets = <&rctl STM32_RESET(APB1, 30U)>;
321 resets = <&rctl STM32_RESET(APB1, 31U)>;
[all …]
/Zephyr-latest/dts/arm/st/l1/
Dstm32l1.dtsi110 rctl: reset-controller { label
111 compatible = "st,stm32-rcc-rctl";
131 resets = <&rctl STM32_RESET(APB1, 17U)>;
140 resets = <&rctl STM32_RESET(APB1, 18U)>;
149 resets = <&rctl STM32_RESET(APB1, 19U)>;
158 resets = <&rctl STM32_RESET(APB1, 20U)>;
211 resets = <&rctl STM32_RESET(APB2, 14U)>;
261 resets = <&rctl STM32_RESET(APB1, 0U)>;
283 resets = <&rctl STM32_RESET(APB1, 1U)>;
305 resets = <&rctl STM32_RESET(APB1, 2U)>;
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f3.dtsi102 rctl: reset-controller { label
103 compatible = "st,stm32-rcc-rctl";
188 resets = <&rctl STM32_RESET(APB2, 14U)>;
197 resets = <&rctl STM32_RESET(APB1, 17U)>;
206 resets = <&rctl STM32_RESET(APB1, 18U)>;
215 resets = <&rctl STM32_RESET(APB1, 19U)>;
270 resets = <&rctl STM32_RESET(APB1, 0U)>;
292 resets = <&rctl STM32_RESET(APB1, 1U)>;
314 resets = <&rctl STM32_RESET(APB1, 4U)>;
330 resets = <&rctl STM32_RESET(APB1, 5U)>;
[all …]
Dstm32f303.dtsi59 resets = <&rctl STM32_RESET(APB1, 20U)>;
79 resets = <&rctl STM32_RESET(APB2, 11U)>;
96 resets = <&rctl STM32_RESET(APB1, 2U)>;
113 resets = <&rctl STM32_RESET(APB2, 13U)>;
130 resets = <&rctl STM32_RESET(APB2, 20U)>;
/Zephyr-latest/dts/arm/st/mp1/
Dstm32mp157.dtsi50 rctl: reset-controller { label
51 compatible = "st,stm32-rcc-rctl";
269 resets = <&rctl STM32_RESET(APB1, 14U)>;
278 resets = <&rctl STM32_RESET(APB1, 15U)>;
287 resets = <&rctl STM32_RESET(APB1, 16U)>;
296 resets = <&rctl STM32_RESET(APB1, 17U)>;
305 resets = <&rctl STM32_RESET(APB2, 13U)>;
314 resets = <&rctl STM32_RESET(APB1, 18U)>;
323 resets = <&rctl STM32_RESET(APB1, 19U)>;
344 resets = <&rctl STM32_RESET(APB1, 1U)>;
[all …]
/Zephyr-latest/dts/arm/st/h7rs/
Dstm32h7rs.dtsi198 rctl: reset-controller { label
199 compatible = "st,stm32-rcc-rctl";
333 resets = <&rctl STM32_RESET(APB2, 4U)>;
341 resets = <&rctl STM32_RESET(APB1L, 17U)>;
349 resets = <&rctl STM32_RESET(APB1L, 18U)>;
357 resets = <&rctl STM32_RESET(APB1L, 19U)>;
365 resets = <&rctl STM32_RESET(APB1L, 20U)>;
373 resets = <&rctl STM32_RESET(APB1L, 30U)>;
381 resets = <&rctl STM32_RESET(APB1L, 31U)>;
390 resets = <&rctl STM32_RESET(APB4, 3U)>;
[all …]
/Zephyr-latest/dts/arm/st/g4/
Dstm32g4.dtsi179 rctl: reset-controller { label
180 compatible = "st,stm32-rcc-rctl";
267 resets = <&rctl STM32_RESET(APB2, 14U)>;
276 resets = <&rctl STM32_RESET(APB1L, 17U)>;
285 resets = <&rctl STM32_RESET(APB1L, 18U)>;
294 resets = <&rctl STM32_RESET(APB1L, 19U)>;
303 resets = <&rctl STM32_RESET(APB1H, 0U)>;
414 resets = <&rctl STM32_RESET(APB2, 11U)>;
431 resets = <&rctl STM32_RESET(APB1L, 0U)>;
453 resets = <&rctl STM32_RESET(APB1L, 1U)>;
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f412.dtsi55 resets = <&rctl STM32_RESET(APB1, 18U)>;
97 resets = <&rctl STM32_RESET(APB1, 5U)>;
113 resets = <&rctl STM32_RESET(APB2, 1U)>;
136 resets = <&rctl STM32_RESET(APB1, 6U)>;
158 resets = <&rctl STM32_RESET(APB1, 7U)>;
180 resets = <&rctl STM32_RESET(APB1, 8U)>;
Dstm32f4.dtsi131 rctl: reset-controller { label
132 compatible = "st,stm32-rcc-rctl";
241 resets = <&rctl STM32_RESET(APB2, 4U)>;
250 resets = <&rctl STM32_RESET(APB1, 17U)>;
259 resets = <&rctl STM32_RESET(APB2, 5U)>;
328 resets = <&rctl STM32_RESET(APB2, 0U)>;
351 resets = <&rctl STM32_RESET(APB1, 0U)>;
379 resets = <&rctl STM32_RESET(APB1, 1U)>;
407 resets = <&rctl STM32_RESET(APB1, 2U)>;
435 resets = <&rctl STM32_RESET(APB1, 3U)>;
[all …]
/Zephyr-latest/dts/arm/st/l5/
Dstm32l5.dtsi153 rctl: reset-controller { label
154 compatible = "st,stm32-rcc-rctl";
268 resets = <&rctl STM32_RESET(APB2, 14U)>;
277 resets = <&rctl STM32_RESET(APB1L, 17U)>;
286 resets = <&rctl STM32_RESET(APB1L, 18U)>;
295 resets = <&rctl STM32_RESET(APB1L, 19U)>;
304 resets = <&rctl STM32_RESET(APB1L, 20U)>;
313 resets = <&rctl STM32_RESET(APB1H, 0U)>;
402 resets = <&rctl STM32_RESET(AHB2, 22U)>;
473 resets = <&rctl STM32_RESET(APB2, 11U)>;
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7.dtsi158 rctl: reset-controller { label
159 compatible = "st,stm32-rcc-rctl";
292 resets = <&rctl STM32_RESET(APB2, 4U)>;
300 resets = <&rctl STM32_RESET(APB1L, 17U)>;
308 resets = <&rctl STM32_RESET(APB1L, 18U)>;
316 resets = <&rctl STM32_RESET(APB1L, 19U)>;
324 resets = <&rctl STM32_RESET(APB1L, 20U)>;
332 resets = <&rctl STM32_RESET(APB2, 5U)>;
340 resets = <&rctl STM32_RESET(APB1L, 30U)>;
348 resets = <&rctl STM32_RESET(APB1L, 31U)>;
[all …]
/Zephyr-latest/dts/arm/st/c0/
Dstm32c0.dtsi108 rctl: reset-controller { label
109 compatible = "st,stm32-rcc-rctl";
194 resets = <&rctl STM32_RESET(APB1H, 14U)>;
203 resets = <&rctl STM32_RESET(APB1L, 17U)>;
212 resets = <&rctl STM32_RESET(APB1H, 11U)>;
229 resets = <&rctl STM32_RESET(APB1L, 1U)>;
246 resets = <&rctl STM32_RESET(APB1H, 15U)>;
263 resets = <&rctl STM32_RESET(APB1H, 17U)>;
280 resets = <&rctl STM32_RESET(APB1H, 18U)>;
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5.dtsi183 rctl: reset-controller { label
184 compatible = "st,stm32-rcc-rctl";
316 resets = <&rctl STM32_RESET(APB2, 14U)>;
325 resets = <&rctl STM32_RESET(APB1L, 17U)>;
334 resets = <&rctl STM32_RESET(APB1L, 18U)>;
343 resets = <&rctl STM32_RESET(APB1L, 19U)>;
352 resets = <&rctl STM32_RESET(APB1L, 20U)>;
361 resets = <&rctl STM32_RESET(APB3, 6U)>;
502 resets = <&rctl STM32_RESET(APB2, 11U)>;
518 resets = <&rctl STM32_RESET(APB1L, 0U)>;
[all …]

12345