1/* 2 * Copyright (c) 2019 Linaro Ltd. 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9#include <arm/armv7-m.dtsi> 10#include <zephyr/dt-bindings/clock/stm32l1_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/adc/adc.h> 15#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 16#include <zephyr/dt-bindings/dma/stm32_dma.h> 17#include <zephyr/dt-bindings/adc/stm32f4_adc.h> 18#include <zephyr/dt-bindings/reset/stm32l1_reset.h> 19#include <freq.h> 20 21/ { 22 chosen { 23 zephyr,flash-controller = &flash; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-m3"; 33 reg = <0>; 34 }; 35 }; 36 37 sram0: memory@20000000 { 38 compatible = "mmio-sram"; 39 }; 40 41 clocks { 42 clk_hse: clk-hse { 43 #clock-cells = <0>; 44 compatible = "st,stm32-hse-clock"; 45 status = "disabled"; 46 }; 47 48 clk_hsi: clk-hsi { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <DT_FREQ_M(16)>; 52 status = "disabled"; 53 }; 54 55 clk_msi: clk-msi { 56 #clock-cells = <0>; 57 compatible = "st,stm32l0-msi-clock"; 58 msi-range = <5>; /* 2.1MHz (reset value) */ 59 status = "disabled"; 60 }; 61 62 clk_lse: clk-lse { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <32768>; 66 status = "disabled"; 67 }; 68 69 clk_lsi: clk-lsi { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <DT_FREQ_K(37)>; 73 status = "disabled"; 74 }; 75 76 pll: pll { 77 #clock-cells = <0>; 78 compatible = "st,stm32l0-pll-clock"; 79 status = "disabled"; 80 }; 81 }; 82 83 soc { 84 85 flash: flash-controller@40023c00 { 86 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; 87 reg = <0x40023c00 0x400>; 88 interrupts = <4 0>; 89 clocks = <&rcc STM32_CLOCK(AHB1, 15U)>; 90 91 #address-cells = <1>; 92 #size-cells = <1>; 93 94 flash0: flash@8000000 { 95 compatible = "st,stm32f4-nv-flash", "st,stm32-nv-flash", 96 "soc-nv-flash"; 97 98 write-block-size = <4>; 99 /* maximum erase time(ms) for a 128B half-page 100 */ 101 max-erase-time = <4>; 102 }; 103 }; 104 105 rcc: rcc@40023800 { 106 compatible = "st,stm32-rcc"; 107 #clock-cells = <2>; 108 reg = <0x40023800 0x400>; 109 110 rctl: reset-controller { 111 compatible = "st,stm32-rcc-rctl"; 112 #reset-cells = <1>; 113 }; 114 }; 115 116 rtc: rtc@40002800 { 117 compatible = "st,stm32-rtc"; 118 reg = <0x40002800 0x400>; 119 interrupts = <41 0>; 120 clocks = <&rcc STM32_CLOCK(APB1, 28U)>; 121 prescaler = <32768>; 122 alarms-count = <2>; 123 alrm-exti-line = <17>; 124 status = "disabled"; 125 }; 126 127 usart2: serial@40004400 { 128 compatible = "st,stm32-usart", "st,stm32-uart"; 129 reg = <0x40004400 0x400>; 130 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 131 resets = <&rctl STM32_RESET(APB1, 17U)>; 132 interrupts = <38 0>; 133 status = "disabled"; 134 }; 135 136 usart3: serial@40004800 { 137 compatible = "st,stm32-usart", "st,stm32-uart"; 138 reg = <0x40004800 0x400>; 139 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 140 resets = <&rctl STM32_RESET(APB1, 18U)>; 141 interrupts = <39 0>; 142 status = "disabled"; 143 }; 144 145 uart4: serial@40004c00 { 146 compatible = "st,stm32-uart"; 147 reg = <0x40004c00 0x400>; 148 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 149 resets = <&rctl STM32_RESET(APB1, 19U)>; 150 interrupts = <48 0>; 151 status = "disabled"; 152 }; 153 154 uart5: serial@40005000 { 155 compatible = "st,stm32-uart"; 156 reg = <0x40005000 0x400>; 157 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 158 resets = <&rctl STM32_RESET(APB1, 20U)>; 159 interrupts = <49 0>; 160 status = "disabled"; 161 }; 162 163 i2c1: i2c@40005400 { 164 compatible = "st,stm32-i2c-v1"; 165 clock-frequency = <I2C_BITRATE_STANDARD>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 reg = <0x40005400 0x400>; 169 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 170 interrupts = <31 0>, <32 0>; 171 interrupt-names = "event", "error"; 172 status = "disabled"; 173 }; 174 175 i2c2: i2c@40005800 { 176 compatible = "st,stm32-i2c-v1"; 177 clock-frequency = <I2C_BITRATE_STANDARD>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 reg = <0x40005800 0x400>; 181 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 182 interrupts = <33 0>, <34 0>; 183 interrupt-names = "event", "error"; 184 status = "disabled"; 185 }; 186 187 spi1: spi@40013000 { 188 compatible = "st,stm32-spi"; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 reg = <0x40013000 0x400>; 192 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 193 interrupts = <35 0>; 194 status = "disabled"; 195 }; 196 197 spi2: spi@40003800 { 198 compatible = "st,stm32-spi"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 reg = <0x40003800 0x400>; 202 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 203 interrupts = <36 0>; 204 status = "disabled"; 205 }; 206 207 usart1: serial@40013800 { 208 compatible = "st,stm32-usart", "st,stm32-uart"; 209 reg = <0x40013800 0x400>; 210 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 211 resets = <&rctl STM32_RESET(APB2, 14U)>; 212 interrupts = <37 0>; 213 status = "disabled"; 214 }; 215 216 adc1: adc@40012400 { 217 compatible = "st,stm32f4-adc", "st,stm32-adc"; 218 reg = <0x40012400 0x400>; 219 clocks = <&rcc STM32_CLOCK(APB2, 9U)>, 220 <&rcc STM32_SRC_HSI NO_SEL>; 221 interrupts = <18 0>; 222 status = "disabled"; 223 #io-channel-cells = <1>; 224 resolutions = <STM32_ADC_RES(12, 0x00) 225 STM32_ADC_RES(10, 0x01) 226 STM32_ADC_RES(8, 0x02) 227 STM32_ADC_RES(6, 0x03)>; 228 sampling-times = <4 9 16 24 48 96 192 384>; 229 st,adc-clock-source = "ASYNC"; 230 st,adc-sequencer = "FULLY_CONFIGURABLE"; 231 st,adc-oversampler = "OVERSAMPLER_NONE"; 232 }; 233 234 dac1: dac@40007400 { 235 compatible = "st,stm32-dac"; 236 reg = <0x40007400 0x400>; 237 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 238 status = "disabled"; 239 #io-channel-cells = <1>; 240 }; 241 242 exti: interrupt-controller@40010400 { 243 compatible = "st,stm32-exti"; 244 interrupt-controller; 245 #interrupt-cells = <1>; 246 #address-cells = <1>; 247 reg = <0x40010400 0x400>; 248 num-lines = <16>; 249 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 250 <10 0>, <23 0>, <40 0>; 251 interrupt-names = "line0", "line1", "line2", "line3", 252 "line4", "line5-9", "line10-15"; 253 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 254 <4 1>, <5 5>, <10 6>; 255 }; 256 257 timers2: timers@40000000 { 258 compatible = "st,stm32-timers"; 259 reg = <0x40000000 0x400>; 260 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 261 resets = <&rctl STM32_RESET(APB1, 0U)>; 262 interrupts = <28 0>; 263 interrupt-names = "global"; 264 st,prescaler = <0>; 265 status = "disabled"; 266 267 pwm { 268 compatible = "st,stm32-pwm"; 269 status = "disabled"; 270 #pwm-cells = <3>; 271 }; 272 273 counter { 274 compatible = "st,stm32-counter"; 275 status = "disabled"; 276 }; 277 }; 278 279 timers3: timers@40000400 { 280 compatible = "st,stm32-timers"; 281 reg = <0x40000400 0x400>; 282 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 283 resets = <&rctl STM32_RESET(APB1, 1U)>; 284 interrupts = <29 0>; 285 interrupt-names = "global"; 286 st,prescaler = <0>; 287 status = "disabled"; 288 289 pwm { 290 compatible = "st,stm32-pwm"; 291 status = "disabled"; 292 #pwm-cells = <3>; 293 }; 294 295 counter { 296 compatible = "st,stm32-counter"; 297 status = "disabled"; 298 }; 299 }; 300 301 timers4: timers@40000800 { 302 compatible = "st,stm32-timers"; 303 reg = <0x40000800 0x400>; 304 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 305 resets = <&rctl STM32_RESET(APB1, 2U)>; 306 interrupts = <30 0>; 307 interrupt-names = "global"; 308 st,prescaler = <0>; 309 status = "disabled"; 310 311 pwm { 312 compatible = "st,stm32-pwm"; 313 status = "disabled"; 314 #pwm-cells = <3>; 315 }; 316 317 counter { 318 compatible = "st,stm32-counter"; 319 status = "disabled"; 320 }; 321 }; 322 323 timers9: timers@40010800 { 324 compatible = "st,stm32-timers"; 325 reg = <0x40010800 0x400>; 326 clocks = <&rcc STM32_CLOCK(APB2, 2U)>; 327 resets = <&rctl STM32_RESET(APB2, 2U)>; 328 interrupts = <25 0>; 329 interrupt-names = "global"; 330 st,prescaler = <0>; 331 status = "disabled"; 332 333 pwm { 334 compatible = "st,stm32-pwm"; 335 status = "disabled"; 336 #pwm-cells = <3>; 337 }; 338 339 counter { 340 compatible = "st,stm32-counter"; 341 status = "disabled"; 342 }; 343 }; 344 345 timers10: timers@40010c00 { 346 compatible = "st,stm32-timers"; 347 reg = <0x40010c00 0x400>; 348 clocks = <&rcc STM32_CLOCK(APB2, 3U)>; 349 resets = <&rctl STM32_RESET(APB2, 3U)>; 350 interrupts = <26 0>; 351 interrupt-names = "global"; 352 st,prescaler = <0>; 353 status = "disabled"; 354 355 pwm { 356 compatible = "st,stm32-pwm"; 357 status = "disabled"; 358 #pwm-cells = <3>; 359 }; 360 361 counter { 362 compatible = "st,stm32-counter"; 363 status = "disabled"; 364 }; 365 }; 366 367 timers11: timers@40011000 { 368 compatible = "st,stm32-timers"; 369 reg = <0x40011000 0x400>; 370 clocks = <&rcc STM32_CLOCK(APB2, 4U)>; 371 resets = <&rctl STM32_RESET(APB2, 4U)>; 372 interrupts = <27 0>; 373 interrupt-names = "global"; 374 st,prescaler = <0>; 375 status = "disabled"; 376 377 pwm { 378 compatible = "st,stm32-pwm"; 379 status = "disabled"; 380 #pwm-cells = <3>; 381 }; 382 383 counter { 384 compatible = "st,stm32-counter"; 385 status = "disabled"; 386 }; 387 }; 388 389 pinctrl: pin-controller@40020000 { 390 compatible = "st,stm32-pinctrl"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 reg = <0x40020000 0x2000>; 394 395 gpioa: gpio@40020000 { 396 compatible = "st,stm32-gpio"; 397 gpio-controller; 398 #gpio-cells = <2>; 399 reg = <0x40020000 0x400>; 400 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 401 }; 402 403 gpiob: gpio@40020400 { 404 compatible = "st,stm32-gpio"; 405 gpio-controller; 406 #gpio-cells = <2>; 407 reg = <0x40020400 0x400>; 408 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 409 }; 410 411 gpioc: gpio@40020800 { 412 compatible = "st,stm32-gpio"; 413 gpio-controller; 414 #gpio-cells = <2>; 415 reg = <0x40020800 0x400>; 416 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 417 }; 418 419 gpiod: gpio@40020c00 { 420 compatible = "st,stm32-gpio"; 421 gpio-controller; 422 #gpio-cells = <2>; 423 reg = <0x40020c00 0x400>; 424 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; 425 }; 426 427 gpioe: gpio@40021000 { 428 compatible = "st,stm32-gpio"; 429 gpio-controller; 430 #gpio-cells = <2>; 431 reg = <0x40021000 0x400>; 432 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; 433 }; 434 435 gpioh: gpio@40021400 { 436 compatible = "st,stm32-gpio"; 437 gpio-controller; 438 #gpio-cells = <2>; 439 reg = <0x40021400 0x400>; 440 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 441 }; 442 }; 443 444 iwdg: watchdog@40003000 { 445 compatible = "st,stm32-watchdog"; 446 reg = <0x40003000 0x400>; 447 status = "disabled"; 448 }; 449 450 wwdg: watchdog@40002c00 { 451 compatible = "st,stm32-window-watchdog"; 452 reg = <0x40002C00 0x400>; 453 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 454 interrupts = <0 7>; 455 status = "disabled"; 456 }; 457 458 eeprom: eeprom@8080000{ 459 compatible = "st,stm32-eeprom"; 460 status = "disabled"; 461 }; 462 463 dma1: dma@40026000 { 464 compatible = "st,stm32-dma-v2bis"; 465 #dma-cells = <2>; 466 reg = <0x40026000 0x400>; 467 clocks = <&rcc STM32_CLOCK(AHB1, 24U)>; 468 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; 469 status = "disabled"; 470 }; 471 }; 472 473 die_temp: dietemp { 474 compatible = "st,stm32-temp-cal"; 475 ts-cal1-addr = <0x1FF800FA>; 476 ts-cal2-addr = <0x1FF800FE>; 477 ts-cal1-temp = <30>; 478 ts-cal2-temp = <110>; 479 ts-cal-vrefanalog = <3000>; 480 io-channels = <&adc1 16>; 481 status = "disabled"; 482 }; 483 484 vref: vref { 485 compatible = "st,stm32-vref"; 486 vrefint-cal-addr = <0x1FF800F8>; 487 vrefint-cal-mv = <3000>; 488 io-channels = <&adc1 17>; 489 status = "disabled"; 490 }; 491 492 smbus1: smbus1 { 493 compatible = "st,stm32-smbus"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 i2c = <&i2c1>; 497 status = "disabled"; 498 }; 499 500 smbus2: smbus2 { 501 compatible = "st,stm32-smbus"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 i2c = <&i2c2>; 505 status = "disabled"; 506 }; 507}; 508 509&nvic { 510 arm,num-irq-priority-bits = <4>; 511}; 512
