1/*
2 * Copyright (c) 2017 I-SENSE group of ICCS
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 * Copyright (c) 2024 STMicroelectronics
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include <arm/armv7-m.dtsi>
10#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/gpio/gpio.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15#include <zephyr/dt-bindings/dma/stm32_dma.h>
16#include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
17#include <zephyr/dt-bindings/adc/adc.h>
18#include <freq.h>
19
20/ {
21	chosen {
22		zephyr,flash-controller = &flash;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-m4f";
32			reg = <0>;
33		};
34	};
35
36	sram0: memory@20000000 {
37		compatible = "mmio-sram";
38	};
39
40
41	clocks {
42		clk_hse: clk-hse {
43			#clock-cells = <0>;
44			compatible = "st,stm32-hse-clock";
45			status = "disabled";
46		};
47
48		clk_hsi: clk-hsi {
49			#clock-cells = <0>;
50			compatible = "fixed-clock";
51			clock-frequency = <DT_FREQ_M(8)>;
52			status = "disabled";
53		};
54
55		clk_lse: clk-lse {
56			#clock-cells = <0>;
57			compatible = "st,stm32-lse-clock";
58			clock-frequency = <32768>;
59			driving-capability = <0>;
60			status = "disabled";
61		};
62
63		clk_lsi: clk-lsi {
64			#clock-cells = <0>;
65			compatible = "fixed-clock";
66			clock-frequency = <DT_FREQ_K(40)>;
67			status = "disabled";
68		};
69
70		pll: pll {
71			#clock-cells = <0>;
72			compatible = "st,stm32f0-pll-clock";
73			status = "disabled";
74		};
75	};
76
77	soc {
78		flash: flash-controller@40022000 {
79			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
80			reg = <0x40022000 0x400>;
81			interrupts = <4 0>;
82			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
83
84			#address-cells = <1>;
85			#size-cells = <1>;
86
87			flash0: flash@8000000 {
88				compatible = "st,stm32-nv-flash", "soc-nv-flash";
89
90				write-block-size = <2>;
91				erase-block-size = <2048>;
92				/* maximum erase time for a 2K sector */
93				max-erase-time = <40>;
94			};
95		};
96
97		rcc: rcc@40021000 {
98			compatible = "st,stm32f3-rcc";
99			#clock-cells = <2>;
100			reg = <0x40021000 0x400>;
101
102			rctl: reset-controller {
103				compatible = "st,stm32-rcc-rctl";
104				#reset-cells = <1>;
105			};
106		};
107
108		exti: interrupt-controller@40010400 {
109			compatible = "st,stm32-exti";
110			interrupt-controller;
111			#interrupt-cells = <1>;
112			#address-cells = <1>;
113			reg = <0x40010400 0x400>;
114			num-lines = <16>;
115			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
116				     <10 0>, <23 0>, <40 0>;
117			interrupt-names = "line0", "line1", "line2", "line3",
118					  "line4", "line5-9", "line10-15";
119			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
120				      <4 1>, <5 5>, <10 6>;
121		};
122
123		pinctrl: pin-controller@48000000 {
124			compatible = "st,stm32-pinctrl";
125			#address-cells = <1>;
126			#size-cells = <1>;
127			reg = <0x48000000 0x1800>;
128
129			gpioa: gpio@48000000 {
130				compatible = "st,stm32-gpio";
131				gpio-controller;
132				#gpio-cells = <2>;
133				reg = <0x48000000 0x400>;
134				clocks = <&rcc STM32_CLOCK(AHB1, 17U)>;
135			};
136
137			gpiob: gpio@48000400 {
138				compatible = "st,stm32-gpio";
139				gpio-controller;
140				#gpio-cells = <2>;
141				reg = <0x48000400 0x400>;
142				clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
143			};
144
145			gpioc: gpio@48000800 {
146				compatible = "st,stm32-gpio";
147				gpio-controller;
148				#gpio-cells = <2>;
149				reg = <0x48000800 0x400>;
150				clocks = <&rcc STM32_CLOCK(AHB1, 19U)>;
151			};
152
153			gpiod: gpio@48000c00 {
154				compatible = "st,stm32-gpio";
155				gpio-controller;
156				#gpio-cells = <2>;
157				reg = <0x48000c00 0x400>;
158				clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;
159			};
160
161			gpiof: gpio@48001400 {
162				compatible = "st,stm32-gpio";
163				gpio-controller;
164				#gpio-cells = <2>;
165				reg = <0x48001400 0x400>;
166				clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
167			};
168		};
169
170		iwdg: watchdog@40003000 {
171			compatible = "st,stm32-watchdog";
172			reg = <0x40003000 0x400>;
173			status = "disabled";
174		};
175
176		wwdg: watchdog@40002c00 {
177			compatible = "st,stm32-window-watchdog";
178			reg = <0x40002C00 0x400>;
179			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
180			interrupts = <0 7>;
181			status = "disabled";
182		};
183
184		usart1: serial@40013800 {
185			compatible = "st,stm32-usart", "st,stm32-uart";
186			reg = <0x40013800 0x400>;
187			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
188			resets = <&rctl STM32_RESET(APB2, 14U)>;
189			interrupts = <37 0>;
190			status = "disabled";
191		};
192
193		usart2: serial@40004400 {
194			compatible = "st,stm32-usart", "st,stm32-uart";
195			reg = <0x40004400 0x400>;
196			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
197			resets = <&rctl STM32_RESET(APB1, 17U)>;
198			interrupts = <38 0>;
199			status = "disabled";
200		};
201
202		usart3: serial@40004800 {
203			compatible = "st,stm32-usart", "st,stm32-uart";
204			reg = <0x40004800 0x400>;
205			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
206			resets = <&rctl STM32_RESET(APB1, 18U)>;
207			interrupts = <39 0>;
208			status = "disabled";
209		};
210
211		uart4: serial@40004c00 {
212			compatible = "st,stm32-uart";
213			reg = <0x40004c00 0x400>;
214			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
215			resets = <&rctl STM32_RESET(APB1, 19U)>;
216			interrupts = <52 0>;
217			status = "disabled";
218		};
219
220		i2c1: i2c@40005400 {
221			compatible = "st,stm32-i2c-v2";
222			clock-frequency = <I2C_BITRATE_STANDARD>;
223			#address-cells = <1>;
224			#size-cells = <0>;
225			reg = <0x40005400 0x400>;
226			clocks = <&rcc STM32_CLOCK(APB1, 21U)>,
227				 /* I2C clock source should always be defined,
228				  * even for the default value
229				  */
230				 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
231			interrupts = <31 0>, <32 0>;
232			interrupt-names = "event", "error";
233			status = "disabled";
234		};
235
236		spi1: spi@40013000 {
237			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
238			#address-cells = <1>;
239			#size-cells = <0>;
240			reg = <0x40013000 0x400>;
241			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
242			interrupts = <35 5>;
243			status = "disabled";
244		};
245
246		dac1: dac@40007400 {
247			compatible = "st,stm32-dac";
248			reg = <0x40007400 0x400>;
249			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
250			status = "disabled";
251			#io-channel-cells = <1>;
252		};
253
254		usb: usb@40005c00 {
255			compatible = "st,stm32-usb";
256			reg = <0x40005c00 0x400>;
257			interrupts = <20 0>;
258			interrupt-names = "usb";
259			num-bidir-endpoints = <8>;
260			ram-size = <512>;
261			phys = <&usb_fs_phy>;
262			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
263			status = "disabled";
264		};
265
266		timers2: timers@40000000 {
267			compatible = "st,stm32-timers";
268			reg = <0x40000000 0x400>;
269			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
270			resets = <&rctl STM32_RESET(APB1, 0U)>;
271			interrupts = <28 0>;
272			interrupt-names = "global";
273			st,prescaler = <0>;
274			status = "disabled";
275
276			pwm {
277				compatible = "st,stm32-pwm";
278				status = "disabled";
279				#pwm-cells = <3>;
280			};
281
282			counter {
283				compatible = "st,stm32-counter";
284				status = "disabled";
285			};
286		};
287
288		timers3: timers@40000400 {
289			compatible = "st,stm32-timers";
290			reg = <0x40000400 0x400>;
291			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
292			resets = <&rctl STM32_RESET(APB1, 1U)>;
293			interrupts = <29 0>;
294			interrupt-names = "global";
295			st,prescaler = <0>;
296			status = "disabled";
297
298			pwm {
299				compatible = "st,stm32-pwm";
300				status = "disabled";
301				#pwm-cells = <3>;
302			};
303
304			counter {
305				compatible = "st,stm32-counter";
306				status = "disabled";
307			};
308		};
309
310		timers6: timers@40001000 {
311			compatible = "st,stm32-timers";
312			reg = <0x40001000 0x400>;
313			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
314			resets = <&rctl STM32_RESET(APB1, 4U)>;
315			interrupts = <54 0>;
316			interrupt-names = "global";
317			st,prescaler = <0>;
318			status = "disabled";
319
320			counter {
321				compatible = "st,stm32-counter";
322				status = "disabled";
323			};
324		};
325
326		timers7: timers@40001400 {
327			compatible = "st,stm32-timers";
328			reg = <0x40001400 0x400>;
329			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
330			resets = <&rctl STM32_RESET(APB1, 5U)>;
331			interrupts = <55 0>;
332			interrupt-names = "global";
333			st,prescaler = <0>;
334			status = "disabled";
335
336			counter {
337				compatible = "st,stm32-counter";
338				status = "disabled";
339			};
340		};
341
342		timers15: timers@40014000 {
343			compatible = "st,stm32-timers";
344			reg = <0x40014000 0x400>;
345			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
346			resets = <&rctl STM32_RESET(APB2, 16U)>;
347			interrupts = <24 0>;
348			interrupt-names = "global";
349			st,prescaler = <0>;
350			status = "disabled";
351
352			pwm {
353				compatible = "st,stm32-pwm";
354				status = "disabled";
355				#pwm-cells = <3>;
356			};
357
358			counter {
359				compatible = "st,stm32-counter";
360				status = "disabled";
361			};
362		};
363
364		timers16: timers@40014400 {
365			compatible = "st,stm32-timers";
366			reg = <0x40014400 0x400>;
367			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
368			resets = <&rctl STM32_RESET(APB2, 17U)>;
369			interrupts = <25 0>;
370			interrupt-names = "global";
371			st,prescaler = <0>;
372			status = "disabled";
373
374			pwm {
375				compatible = "st,stm32-pwm";
376				status = "disabled";
377				#pwm-cells = <3>;
378			};
379
380			counter {
381				compatible = "st,stm32-counter";
382				status = "disabled";
383			};
384		};
385
386		timers17: timers@40014800 {
387			compatible = "st,stm32-timers";
388			reg = <0x40014800 0x400>;
389			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
390			resets = <&rctl STM32_RESET(APB2, 18U)>;
391			interrupts = <26 0>;
392			interrupt-names = "global";
393			st,prescaler = <0>;
394			status = "disabled";
395
396			pwm {
397				compatible = "st,stm32-pwm";
398				status = "disabled";
399				#pwm-cells = <3>;
400			};
401
402			counter {
403				compatible = "st,stm32-counter";
404				status = "disabled";
405			};
406		};
407
408		rtc: rtc@40002800 {
409			compatible = "st,stm32-rtc";
410			reg = <0x40002800 0x400>;
411			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
412			interrupts = <41 0>;
413			prescaler = <32768>;
414			alarms-count = <2>;
415			alrm-exti-line = <17>;
416			status = "disabled";
417		};
418
419		can1: can@40006400 {
420			compatible = "st,stm32-bxcan";
421			reg = <0x40006400 0x400>;
422			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
423			interrupt-names = "TX", "RX0", "RX1", "SCE";
424			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
425			status = "disabled";
426		};
427
428		dma1: dma@40020000 {
429			compatible = "st,stm32-dma-v2bis";
430			#dma-cells = <2>;
431			reg = <0x40020000 0x400>;
432			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
433			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
434			status = "disabled";
435		};
436	};
437
438	die_temp: dietemp {
439		compatible = "st,stm32-temp-cal";
440		ts-cal1-addr = <0x1FFFF7B8>;
441		ts-cal2-addr = <0x1FFFF7C2>;
442		ts-cal1-temp = <30>;
443		ts-cal2-temp = <110>;
444		ts-cal-vrefanalog = <3300>;
445		io-channels = <&adc1 16>;
446		status = "disabled";
447	};
448
449	vref: vref {
450		compatible = "st,stm32-vref";
451		vrefint-cal-addr = <0x1FFFF7BA>;
452		vrefint-cal-mv = <3300>;
453		io-channels = <&adc1 18>;
454		status = "disabled";
455	};
456
457	vbat: vbat {
458		compatible = "st,stm32-vbat";
459		ratio = <2>;
460		io-channels = <&adc1 17>;
461		status = "disabled";
462	};
463
464	usb_fs_phy: usbphy {
465		compatible = "usb-nop-xceiv";
466		#phy-cells = <0>;
467	};
468
469	smbus1: smbus1 {
470		compatible = "st,stm32-smbus";
471		#address-cells = <1>;
472		#size-cells = <0>;
473		i2c = <&i2c1>;
474		status = "disabled";
475	};
476};
477
478&nvic {
479	arm,num-irq-priority-bits = <4>;
480};
481