1/*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
14#include <zephyr/dt-bindings/dma/stm32_dma.h>
15#include <zephyr/dt-bindings/adc/stm32f1_adc.h>
16#include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
17#include <zephyr/dt-bindings/adc/adc.h>
18#include <freq.h>
19
20/ {
21	chosen {
22		zephyr,flash-controller = &flash;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-m3";
32			reg = <0>;
33		};
34	};
35
36	sram0: memory@20000000 {
37		compatible = "mmio-sram";
38	};
39
40	clocks {
41		clk_hse: clk-hse {
42			#clock-cells = <0>;
43			compatible = "st,stm32-hse-clock";
44			status = "disabled";
45		};
46
47		clk_hsi: clk-hsi {
48			#clock-cells = <0>;
49			compatible = "fixed-clock";
50			clock-frequency = <DT_FREQ_M(8)>;
51			status = "disabled";
52		};
53
54		clk_lse: clk-lse {
55			#clock-cells = <0>;
56			compatible = "fixed-clock";
57			clock-frequency = <32768>;
58			status = "disabled";
59		};
60
61		clk_lsi: clk-lsi {
62			#clock-cells = <0>;
63			compatible = "fixed-clock";
64			clock-frequency = <DT_FREQ_K(40)>;
65			status = "disabled";
66		};
67
68		pll: pll {
69			#clock-cells = <0>;
70			compatible = "st,stm32f1-pll-clock";
71			status = "disabled";
72		};
73	};
74
75	mcos {
76		mco1: mco1 {
77			compatible = "st,stm32f1-clock-mco";
78			status = "disabled";
79		};
80	};
81
82	soc {
83
84		flash: flash-controller@40022000 {
85			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
86			reg = <0x40022000 0x400>;
87			interrupts = <3 0>;
88			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
89
90			#address-cells = <1>;
91			#size-cells = <1>;
92
93			flash0: flash@8000000 {
94				compatible = "st,stm32-nv-flash", "soc-nv-flash";
95
96				write-block-size = <2>;
97				/* maximum erase time for a 2K sector */
98				max-erase-time = <40>;
99			};
100		};
101
102		rcc: rcc@40021000 {
103			compatible = "st,stm32f1-rcc";
104			#clock-cells = <2>;
105			reg = <0x40021000 0x400>;
106
107			rctl: reset-controller {
108				compatible = "st,stm32-rcc-rctl";
109				#reset-cells = <1>;
110			};
111		};
112
113		exti: interrupt-controller@40010400 {
114			compatible = "st,stm32-exti";
115			interrupt-controller;
116			#interrupt-cells = <1>;
117			#address-cells = <1>;
118			reg = <0x40010400 0x400>;
119			num-lines = <16>;
120			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
121				     <10 0>, <23 0>, <40 0>;
122			interrupt-names = "line0", "line1", "line2", "line3",
123					  "line4", "line5-9", "line10-15";
124			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
125				      <4 1>, <5 5>, <10 6>;
126		};
127
128		pinctrl: pin-controller@40010800 {
129			compatible = "st,stm32f1-pinctrl";
130			#address-cells = <1>;
131			#size-cells = <1>;
132			reg = <0x40010800 0x1C00>;
133
134			gpioa: gpio@40010800 {
135				compatible = "st,stm32-gpio";
136				gpio-controller;
137				#gpio-cells = <2>;
138				reg = <0x40010800 0x400>;
139				clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
140			};
141
142			gpiob: gpio@40010c00 {
143				compatible = "st,stm32-gpio";
144				gpio-controller;
145				#gpio-cells = <2>;
146				reg = <0x40010c00 0x400>;
147				clocks = <&rcc STM32_CLOCK(APB2, 3U)>;
148			};
149
150			gpioc: gpio@40011000 {
151				compatible = "st,stm32-gpio";
152				gpio-controller;
153				#gpio-cells = <2>;
154				reg = <0x40011000 0x400>;
155				clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
156			};
157
158			gpiod: gpio@40011400 {
159				compatible = "st,stm32-gpio";
160				gpio-controller;
161				#gpio-cells = <2>;
162				reg = <0x40011400 0x400>;
163				clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
164			};
165
166			gpioe: gpio@40011800 {
167				compatible = "st,stm32-gpio";
168				gpio-controller;
169				#gpio-cells = <2>;
170				reg = <0x40011800 0x400>;
171				clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
172			};
173		};
174
175		usart1: serial@40013800 {
176			compatible = "st,stm32-usart", "st,stm32-uart";
177			reg = <0x40013800 0x400>;
178			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
179			resets = <&rctl STM32_RESET(APB2, 14U)>;
180			interrupts = <37 0>;
181			status = "disabled";
182		};
183
184		usart2: serial@40004400 {
185			compatible = "st,stm32-usart", "st,stm32-uart";
186			reg = <0x40004400 0x400>;
187			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
188			resets = <&rctl STM32_RESET(APB1, 17U)>;
189			interrupts = <38 0>;
190			status = "disabled";
191		};
192
193		usart3: serial@40004800 {
194			compatible = "st,stm32-usart", "st,stm32-uart";
195			reg = <0x40004800 0x400>;
196			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
197			resets = <&rctl STM32_RESET(APB1, 18U)>;
198			interrupts = <39 0>;
199			status = "disabled";
200		};
201
202		i2c1: i2c@40005400 {
203			compatible = "st,stm32-i2c-v1";
204			clock-frequency = <I2C_BITRATE_STANDARD>;
205			#address-cells = <1>;
206			#size-cells = <0>;
207			reg = <0x40005400 0x400>;
208			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
209			interrupts = <31 0>, <32 0>;
210			interrupt-names = "event", "error";
211			status = "disabled";
212		};
213
214		i2c2: i2c@40005800 {
215			compatible = "st,stm32-i2c-v1";
216			clock-frequency = <I2C_BITRATE_STANDARD>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			reg = <0x40005800 0x400>;
220			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
221			interrupts = <33 0>, <34 0>;
222			interrupt-names = "event", "error";
223			status = "disabled";
224		};
225
226		spi1: spi@40013000 {
227			compatible = "st,stm32-spi";
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0x40013000 0x400>;
231			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
232			interrupts = <35 5>;
233			status = "disabled";
234		};
235
236		iwdg: watchdog@40003000 {
237			compatible = "st,stm32-watchdog";
238			reg = <0x40003000 0x400>;
239			status = "disabled";
240		};
241
242		wwdg: watchdog@40002c00 {
243			compatible = "st,stm32-window-watchdog";
244			reg = <0x40002C00 0x400>;
245			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
246			interrupts = <0 7>;
247			status = "disabled";
248		};
249
250		timers1: timers@40012c00 {
251			compatible = "st,stm32-timers";
252			reg = <0x40012c00 0x400>;
253			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
254			resets = <&rctl STM32_RESET(APB2, 11U)>;
255			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
256			interrupt-names = "brk", "up", "trgcom", "cc";
257			st,prescaler = <0>;
258			status = "disabled";
259
260			pwm {
261				compatible = "st,stm32-pwm";
262				status = "disabled";
263				#pwm-cells = <3>;
264			};
265		};
266
267		timers2: timers@40000000 {
268			compatible = "st,stm32-timers";
269			reg = <0x40000000 0x400>;
270			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
271			resets = <&rctl STM32_RESET(APB1, 0U)>;
272			interrupts = <28 0>;
273			interrupt-names = "global";
274			st,prescaler = <0>;
275			status = "disabled";
276
277			pwm {
278				compatible = "st,stm32-pwm";
279				status = "disabled";
280				#pwm-cells = <3>;
281			};
282
283			counter {
284				compatible = "st,stm32-counter";
285				status = "disabled";
286			};
287		};
288
289		timers3: timers@40000400 {
290			compatible = "st,stm32-timers";
291			reg = <0x40000400 0x400>;
292			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
293			resets = <&rctl STM32_RESET(APB1, 1U)>;
294			interrupts = <29 0>;
295			interrupt-names = "global";
296			st,prescaler = <0>;
297			status = "disabled";
298
299			pwm {
300				compatible = "st,stm32-pwm";
301				status = "disabled";
302				#pwm-cells = <3>;
303			};
304
305			counter {
306				compatible = "st,stm32-counter";
307				status = "disabled";
308			};
309		};
310
311		timers4: timers@40000800 {
312			compatible = "st,stm32-timers";
313			reg = <0x40000800 0x400>;
314			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
315			resets = <&rctl STM32_RESET(APB1, 2U)>;
316			interrupts = <30 0>;
317			interrupt-names = "global";
318			st,prescaler = <0>;
319			status = "disabled";
320
321			pwm {
322				compatible = "st,stm32-pwm";
323				status = "disabled";
324				#pwm-cells = <3>;
325			};
326
327			counter {
328				compatible = "st,stm32-counter";
329				status = "disabled";
330			};
331		};
332
333		rtc: rtc@40002800 {
334			compatible = "st,stm32-rtc";
335			reg = <0x40002800 0x400>;
336			interrupts = <41 0>;
337			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
338			prescaler = <32768>;
339			status = "disabled";
340		};
341
342		adc1: adc@40012400 {
343			compatible = "st,stm32f1-adc", "st,stm32-adc";
344			reg = <0x40012400 0x400>;
345			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
346			interrupts = <18 0>;
347			status = "disabled";
348			#io-channel-cells = <1>;
349			resolutions = <STM32F1_ADC_RES(12)>;
350			sampling-times = <2 8 14 29 42 56 72 240>;
351			st,adc-sequencer = "FULLY_CONFIGURABLE";
352			st,adc-oversampler = "OVERSAMPLER_NONE";
353		};
354
355		dma1: dma@40020000 {
356			compatible = "st,stm32-dma-v2bis";
357			#dma-cells = <2>;
358			reg = <0x40020000 0x400>;
359			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
360			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
361			status = "disabled";
362		};
363	};
364
365	die_temp: dietemp {
366		compatible = "st,stm32-temp";
367		io-channels = <&adc1 16>;
368		status = "disabled";
369		avgslope = "4.3";
370		v25 = <1430>;
371		ntc;
372	};
373
374	smbus1: smbus1 {
375		compatible = "st,stm32-smbus";
376		#address-cells = <1>;
377		#size-cells = <0>;
378		i2c = <&i2c1>;
379		status = "disabled";
380	};
381
382	smbus2: smbus2 {
383		compatible = "st,stm32-smbus";
384		#address-cells = <1>;
385		#size-cells = <0>;
386		i2c = <&i2c2>;
387		status = "disabled";
388	};
389};
390
391&nvic {
392	arm,num-irq-priority-bits = <4>;
393};
394