1/*
2 * Copyright (c) 2021 The Chromium OS Authors
3 * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
4 * Copyright (c) 2019 ST Microelectronics
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include <st/g0/stm32g051.dtsi>
10
11/ {
12	soc {
13		compatible = "st,stm32g071", "st,stm32g0", "simple-bus";
14
15		usart3: serial@40004800 {
16			compatible = "st,stm32-usart", "st,stm32-uart";
17			reg = <0x40004800 0x400>;
18			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
19			resets = <&rctl STM32_RESET(APB1L, 18U)>;
20			interrupts = <29 0>;
21			status = "disabled";
22		};
23
24		usart4: serial@40004c00 {
25			compatible = "st,stm32-usart", "st,stm32-uart";
26			reg = <0x40004c00 0x400>;
27			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
28			resets = <&rctl STM32_RESET(APB1L, 19U)>;
29			interrupts = <29 0>;
30			status = "disabled";
31		};
32
33		dmamux1: dmamux@40020800 {
34			dma-requests= <57>;
35		};
36
37		ucpd1: ucpd@4000a000 {
38			compatible = "st,stm32-ucpd";
39			reg = <0x4000a000 0x400>;
40			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
41			interrupts = <8 0>;
42			status = "disabled";
43		};
44
45		ucpd2: ucpd@4000a400 {
46			compatible = "st,stm32-ucpd";
47			reg = <0x4000a400 0x400>;
48			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
49			interrupts = <8 0>;
50			status = "disabled";
51		};
52	};
53};
54