1/* 2 * Copyright (c) 2017 Linaro Limited 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2022 Valerio Setti <vsetti@baylibre.com> 5 * Copyright (c) 2024 STMicroelectronics 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10#include <arm/armv7-m.dtsi> 11#include <zephyr/dt-bindings/adc/adc.h> 12#include <zephyr/dt-bindings/clock/stm32f4_clock.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/gpio/gpio.h> 15#include <zephyr/dt-bindings/pwm/pwm.h> 16#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 17#include <zephyr/dt-bindings/dma/stm32_dma.h> 18#include <zephyr/dt-bindings/adc/stm32f4_adc.h> 19#include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h> 20#include <zephyr/dt-bindings/sensor/qdec_stm32.h> 21#include <freq.h> 22 23/ { 24 chosen { 25 zephyr,flash-controller = &flash; 26 zephyr,cortex-m-idle-timer = &rtc; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-m4f"; 36 reg = <0>; 37 cpu-power-states = <&stop>; 38 }; 39 40 power-states { 41 stop: stop { 42 compatible = "zephyr,power-state"; 43 power-state-name = "suspend-to-idle"; 44 /* It is really hard to establish these numbers precisely. 45 * We are basing on RTC as a wakeup source with 62,5us tick. 46 * It requires a proper margin. Additionally, sys_clock_announce 47 * works within system tick boundaries (100us by default), 48 * which also introduces some shift. 49 */ 50 min-residency-us = <400>; 51 exit-latency-us = <300>; 52 }; 53 }; 54 }; 55 56 sram0: memory@20000000 { 57 compatible = "mmio-sram"; 58 }; 59 60 clocks { 61 clk_hse: clk-hse { 62 #clock-cells = <0>; 63 compatible = "st,stm32-hse-clock"; 64 status = "disabled"; 65 }; 66 67 clk_hsi: clk-hsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <DT_FREQ_M(16)>; 71 status = "disabled"; 72 }; 73 74 clk_lse: clk-lse { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32768>; 78 status = "disabled"; 79 }; 80 81 clk_lsi: clk-lsi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <DT_FREQ_K(32)>; 85 status = "disabled"; 86 }; 87 88 pll: pll { 89 #clock-cells = <0>; 90 compatible = "st,stm32f4-pll-clock"; 91 status = "disabled"; 92 }; 93 }; 94 95 mcos { 96 mco1: mco1 { 97 compatible = "st,stm32-clock-mco"; 98 status = "disabled"; 99 }; 100 101 mco2: mco2 { 102 compatible = "st,stm32-clock-mco"; 103 status = "disabled"; 104 }; 105 }; 106 107 soc { 108 flash: flash-controller@40023c00 { 109 compatible = "st,stm32-flash-controller", "st,stm32f4-flash-controller"; 110 reg = <0x40023c00 0x400>; 111 interrupts = <4 0>; 112 113 #address-cells = <1>; 114 #size-cells = <1>; 115 116 flash0: flash@8000000 { 117 compatible = "st,stm32f4-nv-flash", "st,stm32-nv-flash", 118 "soc-nv-flash"; 119 120 write-block-size = <1>; 121 /* maximum erase time (ms) for a 128K sector */ 122 max-erase-time = <4000>; 123 }; 124 }; 125 126 rcc: rcc@40023800 { 127 compatible = "st,stm32-rcc"; 128 #clock-cells = <2>; 129 reg = <0x40023800 0x400>; 130 131 rctl: reset-controller { 132 compatible = "st,stm32-rcc-rctl"; 133 #reset-cells = <1>; 134 }; 135 }; 136 137 exti: interrupt-controller@40013c00 { 138 compatible = "st,stm32-exti"; 139 interrupt-controller; 140 #interrupt-cells = <1>; 141 #address-cells = <1>; 142 reg = <0x40013c00 0x400>; 143 num-lines = <16>; 144 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 145 <10 0>, <23 0>, <40 0>; 146 interrupt-names = "line0", "line1", "line2", "line3", 147 "line4", "line5-9", "line10-15"; 148 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 149 <4 1>, <5 5>, <10 6>; 150 }; 151 152 pinctrl: pin-controller@40020000 { 153 compatible = "st,stm32-pinctrl"; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 reg = <0x40020000 0x2000>; 157 158 gpioa: gpio@40020000 { 159 compatible = "st,stm32-gpio"; 160 gpio-controller; 161 #gpio-cells = <2>; 162 reg = <0x40020000 0x400>; 163 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 164 }; 165 166 gpiob: gpio@40020400 { 167 compatible = "st,stm32-gpio"; 168 gpio-controller; 169 #gpio-cells = <2>; 170 reg = <0x40020400 0x400>; 171 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 172 }; 173 174 gpioc: gpio@40020800 { 175 compatible = "st,stm32-gpio"; 176 gpio-controller; 177 #gpio-cells = <2>; 178 reg = <0x40020800 0x400>; 179 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 180 }; 181 182 gpiod: gpio@40020c00 { 183 compatible = "st,stm32-gpio"; 184 gpio-controller; 185 #gpio-cells = <2>; 186 reg = <0x40020c00 0x400>; 187 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; 188 }; 189 190 gpioe: gpio@40021000 { 191 compatible = "st,stm32-gpio"; 192 gpio-controller; 193 #gpio-cells = <2>; 194 reg = <0x40021000 0x400>; 195 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; 196 }; 197 198 gpiof: gpio@40021400 { 199 compatible = "st,stm32-gpio"; 200 gpio-controller; 201 #gpio-cells = <2>; 202 reg = <0x40021400 0x400>; 203 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 204 }; 205 206 gpiog: gpio@40021800 { 207 compatible = "st,stm32-gpio"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 reg = <0x40021800 0x400>; 211 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; 212 }; 213 214 gpioh: gpio@40021c00 { 215 compatible = "st,stm32-gpio"; 216 gpio-controller; 217 #gpio-cells = <2>; 218 reg = <0x40021c00 0x400>; 219 clocks = <&rcc STM32_CLOCK(AHB1, 7U)>; 220 }; 221 }; 222 223 iwdg: watchdog@40003000 { 224 compatible = "st,stm32-watchdog"; 225 reg = <0x40003000 0x400>; 226 status = "disabled"; 227 }; 228 229 wwdg: watchdog@40002c00 { 230 compatible = "st,stm32-window-watchdog"; 231 reg = <0x40002C00 0x400>; 232 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 233 interrupts = <0 7>; 234 status = "disabled"; 235 }; 236 237 usart1: serial@40011000 { 238 compatible = "st,stm32-usart", "st,stm32-uart"; 239 reg = <0x40011000 0x400>; 240 clocks = <&rcc STM32_CLOCK(APB2, 4U)>; 241 resets = <&rctl STM32_RESET(APB2, 4U)>; 242 interrupts = <37 0>; 243 status = "disabled"; 244 }; 245 246 usart2: serial@40004400 { 247 compatible = "st,stm32-usart", "st,stm32-uart"; 248 reg = <0x40004400 0x400>; 249 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 250 resets = <&rctl STM32_RESET(APB1, 17U)>; 251 interrupts = <38 0>; 252 status = "disabled"; 253 }; 254 255 usart6: serial@40011400 { 256 compatible = "st,stm32-usart", "st,stm32-uart"; 257 reg = <0x40011400 0x400>; 258 clocks = <&rcc STM32_CLOCK(APB2, 5U)>; 259 resets = <&rctl STM32_RESET(APB2, 5U)>; 260 interrupts = <71 0>; 261 status = "disabled"; 262 }; 263 264 i2c1: i2c@40005400 { 265 compatible = "st,stm32-i2c-v1"; 266 clock-frequency = <I2C_BITRATE_STANDARD>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 reg = <0x40005400 0x400>; 270 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 271 interrupts = <31 0>, <32 0>; 272 interrupt-names = "event", "error"; 273 status = "disabled"; 274 }; 275 276 i2c2: i2c@40005800 { 277 compatible = "st,stm32-i2c-v1"; 278 clock-frequency = <I2C_BITRATE_STANDARD>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 reg = <0x40005800 0x400>; 282 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 283 interrupts = <33 0>, <34 0>; 284 interrupt-names = "event", "error"; 285 status = "disabled"; 286 }; 287 288 i2c3: i2c@40005c00 { 289 compatible = "st,stm32-i2c-v1"; 290 clock-frequency = <I2C_BITRATE_STANDARD>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 reg = <0x40005c00 0x400>; 294 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 295 interrupts = <72 0>, <73 0>; 296 interrupt-names = "event", "error"; 297 status = "disabled"; 298 }; 299 300 spi1: spi@40013000 { 301 compatible = "st,stm32-spi"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <0x40013000 0x400>; 305 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 306 interrupts = <35 5>; 307 status = "disabled"; 308 }; 309 310 usbotg_fs: usb@50000000 { 311 compatible = "st,stm32-otgfs"; 312 reg = <0x50000000 0x40000>; 313 interrupts = <67 0>; 314 interrupt-names = "otgfs"; 315 num-bidir-endpoints = <4>; 316 ram-size = <1280>; 317 maximum-speed = "full-speed"; 318 phys = <&otgfs_phy>; 319 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, 320 <&rcc STM32_SRC_PLL_Q NO_SEL>; 321 status = "disabled"; 322 }; 323 324 timers1: timers@40010000 { 325 compatible = "st,stm32-timers"; 326 reg = <0x40010000 0x400>; 327 clocks = <&rcc STM32_CLOCK(APB2, 0U)>; 328 resets = <&rctl STM32_RESET(APB2, 0U)>; 329 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 330 interrupt-names = "brk", "up", "trgcom", "cc"; 331 st,prescaler = <0>; 332 status = "disabled"; 333 334 pwm { 335 compatible = "st,stm32-pwm"; 336 status = "disabled"; 337 #pwm-cells = <3>; 338 }; 339 340 qdec { 341 compatible = "st,stm32-qdec"; 342 status = "disabled"; 343 st,input-filter-level = <NO_FILTER>; 344 }; 345 }; 346 347 timers2: timers@40000000 { 348 compatible = "st,stm32-timers"; 349 reg = <0x40000000 0x400>; 350 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 351 resets = <&rctl STM32_RESET(APB1, 0U)>; 352 interrupts = <28 0>; 353 interrupt-names = "global"; 354 st,prescaler = <0>; 355 status = "disabled"; 356 357 pwm { 358 compatible = "st,stm32-pwm"; 359 status = "disabled"; 360 #pwm-cells = <3>; 361 }; 362 363 counter { 364 compatible = "st,stm32-counter"; 365 status = "disabled"; 366 }; 367 368 qdec { 369 compatible = "st,stm32-qdec"; 370 status = "disabled"; 371 st,input-filter-level = <NO_FILTER>; 372 }; 373 }; 374 375 timers3: timers@40000400 { 376 compatible = "st,stm32-timers"; 377 reg = <0x40000400 0x400>; 378 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 379 resets = <&rctl STM32_RESET(APB1, 1U)>; 380 interrupts = <29 0>; 381 interrupt-names = "global"; 382 st,prescaler = <0>; 383 status = "disabled"; 384 385 pwm { 386 compatible = "st,stm32-pwm"; 387 status = "disabled"; 388 #pwm-cells = <3>; 389 }; 390 391 counter { 392 compatible = "st,stm32-counter"; 393 status = "disabled"; 394 }; 395 396 qdec { 397 compatible = "st,stm32-qdec"; 398 status = "disabled"; 399 st,input-filter-level = <NO_FILTER>; 400 }; 401 }; 402 403 timers4: timers@40000800 { 404 compatible = "st,stm32-timers"; 405 reg = <0x40000800 0x400>; 406 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 407 resets = <&rctl STM32_RESET(APB1, 2U)>; 408 interrupts = <30 0>; 409 interrupt-names = "global"; 410 st,prescaler = <0>; 411 status = "disabled"; 412 413 pwm { 414 compatible = "st,stm32-pwm"; 415 status = "disabled"; 416 #pwm-cells = <3>; 417 }; 418 419 counter { 420 compatible = "st,stm32-counter"; 421 status = "disabled"; 422 }; 423 424 qdec { 425 compatible = "st,stm32-qdec"; 426 status = "disabled"; 427 st,input-filter-level = <NO_FILTER>; 428 }; 429 }; 430 431 timers5: timers@40000c00 { 432 compatible = "st,stm32-timers"; 433 reg = <0x40000c00 0x400>; 434 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 435 resets = <&rctl STM32_RESET(APB1, 3U)>; 436 interrupts = <50 0>; 437 interrupt-names = "global"; 438 st,prescaler = <0>; 439 status = "disabled"; 440 441 pwm { 442 compatible = "st,stm32-pwm"; 443 status = "disabled"; 444 #pwm-cells = <3>; 445 }; 446 447 counter { 448 compatible = "st,stm32-counter"; 449 status = "disabled"; 450 }; 451 452 qdec { 453 compatible = "st,stm32-qdec"; 454 status = "disabled"; 455 st,input-filter-level = <NO_FILTER>; 456 }; 457 }; 458 459 timers9: timers@40014000 { 460 compatible = "st,stm32-timers"; 461 reg = <0x40014000 0x400>; 462 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 463 resets = <&rctl STM32_RESET(APB2, 16U)>; 464 interrupts = <24 0>; 465 interrupt-names = "global"; 466 st,prescaler = <0>; 467 status = "disabled"; 468 469 pwm { 470 compatible = "st,stm32-pwm"; 471 status = "disabled"; 472 #pwm-cells = <3>; 473 }; 474 475 counter { 476 compatible = "st,stm32-counter"; 477 status = "disabled"; 478 }; 479 }; 480 481 timers10: timers@40014400 { 482 compatible = "st,stm32-timers"; 483 reg = <0x40014400 0x400>; 484 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 485 resets = <&rctl STM32_RESET(APB2, 17U)>; 486 interrupts = <25 0>; 487 interrupt-names = "global"; 488 st,prescaler = <0>; 489 status = "disabled"; 490 491 pwm { 492 compatible = "st,stm32-pwm"; 493 status = "disabled"; 494 #pwm-cells = <3>; 495 }; 496 497 counter { 498 compatible = "st,stm32-counter"; 499 status = "disabled"; 500 }; 501 }; 502 503 timers11: timers@40014800 { 504 compatible = "st,stm32-timers"; 505 reg = <0x40014800 0x400>; 506 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 507 resets = <&rctl STM32_RESET(APB2, 18U)>; 508 interrupts = <26 0>; 509 interrupt-names = "global"; 510 st,prescaler = <0>; 511 status = "disabled"; 512 513 pwm { 514 compatible = "st,stm32-pwm"; 515 status = "disabled"; 516 #pwm-cells = <3>; 517 }; 518 519 counter { 520 compatible = "st,stm32-counter"; 521 status = "disabled"; 522 }; 523 }; 524 525 rtc: rtc@40002800 { 526 compatible = "st,stm32-rtc"; 527 reg = <0x40002800 0x400>; 528 interrupts = <41 0>; 529 clocks = <&rcc STM32_CLOCK(APB1, 28U)>; 530 prescaler = <32768>; 531 alarms-count = <2>; 532 alrm-exti-line = <17>; 533 status = "disabled"; 534 535 bbram: backup_regs { 536 compatible = "st,stm32-bbram"; 537 st,backup-regs = <20>; 538 status = "disabled"; 539 }; 540 }; 541 542 adc1: adc@40012000 { 543 compatible = "st,stm32f4-adc", "st,stm32-adc"; 544 reg = <0x40012000 0x400>; 545 clocks = <&rcc STM32_CLOCK(APB2, 8U)>; 546 interrupts = <18 0>; 547 status = "disabled"; 548 #io-channel-cells = <1>; 549 resolutions = <STM32_ADC_RES(12, 0x00) 550 STM32_ADC_RES(10, 0x01) 551 STM32_ADC_RES(8, 0x02) 552 STM32_ADC_RES(6, 0x03)>; 553 sampling-times = <3 15 28 56 84 112 144 480>; 554 st,adc-clock-source = "SYNC"; 555 st,adc-sequencer = "FULLY_CONFIGURABLE"; 556 st,adc-oversampler = "OVERSAMPLER_NONE"; 557 }; 558 559 dma1: dma@40026000 { 560 compatible = "st,stm32-dma-v1"; 561 #dma-cells = <4>; 562 reg = <0x40026000 0x400>; 563 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; 564 clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; 565 status = "disabled"; 566 }; 567 568 dma2: dma@40026400 { 569 compatible = "st,stm32-dma-v1"; 570 #dma-cells = <4>; 571 reg = <0x40026400 0x400>; 572 interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; 573 clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; 574 st,mem2mem; 575 status = "disabled"; 576 }; 577 578 sdmmc1: sdmmc@40012c00 { 579 compatible = "st,stm32-sdmmc"; 580 reg = <0x40012c00 0x400>; 581 clocks = <&rcc STM32_CLOCK(APB2, 11U)>, 582 <&rcc STM32_SRC_PLL_Q NO_SEL>; 583 resets = <&rctl STM32_RESET(APB2, 11U)>; 584 interrupts = <49 0>; 585 status = "disabled"; 586 }; 587 }; 588 589 die_temp: dietemp { 590 compatible = "st,stm32-temp-cal"; 591 ts-cal1-addr = <0x1FFF7A2C>; 592 ts-cal2-addr = <0x1FFF7A2E>; 593 ts-cal1-temp = <30>; 594 ts-cal2-temp = <110>; 595 ts-cal-vrefanalog = <3300>; 596 io-channels = <&adc1 16>; 597 status = "disabled"; 598 }; 599 600 vref: vref { 601 compatible = "st,stm32-vref"; 602 vrefint-cal-addr = <0x1FFF7A2A>; 603 vrefint-cal-mv = <3300>; 604 io-channels = <&adc1 17>; 605 status = "disabled"; 606 }; 607 608 vbat: vbat { 609 compatible = "st,stm32-vbat"; 610 ratio = <4>; 611 io-channels = <&adc1 18>; 612 status = "disabled"; 613 }; 614 615 otgfs_phy: otgfs_phy { 616 compatible = "usb-nop-xceiv"; 617 #phy-cells = <0>; 618 }; 619 620 smbus1: smbus1 { 621 compatible = "st,stm32-smbus"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 i2c = <&i2c1>; 625 status = "disabled"; 626 }; 627 628 smbus2: smbus2 { 629 compatible = "st,stm32-smbus"; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 i2c = <&i2c2>; 633 status = "disabled"; 634 }; 635 636 smbus3: smbus3 { 637 compatible = "st,stm32-smbus"; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 i2c = <&i2c3>; 641 status = "disabled"; 642 }; 643}; 644 645&nvic { 646 arm,num-irq-priority-bits = <4>; 647}; 648
