1/* 2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/f4/stm32f410.dtsi> 8 9/delete-node/ &dac1; 10/delete-node/ &rng; 11 12/ { 13 clocks { 14 plli2s: plli2s { 15 #clock-cells = <0>; 16 compatible = "st,stm32f411-plli2s-clock"; 17 status = "disabled"; 18 }; 19 20 clk48: clk48 { 21 #clock-cells = <0>; 22 compatible = "st,stm32-clock-mux"; 23 clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; 24 status = "disabled"; 25 }; 26 }; 27 28 soc { 29 compatible = "st,stm32f412", "st,stm32f4", "simple-bus"; 30 31 pinctrl: pin-controller@40020000 { 32 reg = <0x40020000 0x1c00>; 33 34 gpiof: gpio@40021400 { 35 compatible = "st,stm32-gpio"; 36 gpio-controller; 37 #gpio-cells = <2>; 38 reg = <0x40021400 0x400>; 39 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 40 }; 41 42 gpiog: gpio@40021800 { 43 compatible = "st,stm32-gpio"; 44 gpio-controller; 45 #gpio-cells = <2>; 46 reg = <0x40021800 0x400>; 47 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; 48 }; 49 }; 50 51 usart3: serial@40004800 { 52 compatible = "st,stm32-usart", "st,stm32-uart"; 53 reg = <0x40004800 0x400>; 54 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 55 resets = <&rctl STM32_RESET(APB1, 18U)>; 56 interrupts = <39 0>; 57 status = "disabled"; 58 }; 59 60 spi3: spi@40003c00 { 61 compatible = "st,stm32-spi"; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 reg = <0x40003c00 0x400>; 65 clocks = <&rcc STM32_CLOCK(APB1, 15U)>; 66 interrupts = <51 5>; 67 status = "disabled"; 68 }; 69 70 spi4: spi@40013400 { 71 compatible = "st,stm32-spi"; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 reg = <0x40013400 0x400>; 75 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 76 interrupts = <84 5>; 77 status = "disabled"; 78 }; 79 80 i2s4: i2s@40013400 { 81 compatible = "st,stm32-i2s"; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 reg = <0x40013400 0x400>; 85 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 86 interrupts = <84 5>; 87 dmas = <&dma2 1 4 0x400 0x3 88 &dma2 0 4 0x400 0x3>; 89 dma-names = "tx", "rx"; 90 status = "disabled"; 91 }; 92 93 timers7: timers@40001400 { 94 compatible = "st,stm32-timers"; 95 reg = <0x40001400 0x400>; 96 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 97 resets = <&rctl STM32_RESET(APB1, 5U)>; 98 interrupts = <55 0>; 99 interrupt-names = "global"; 100 st,prescaler = <0>; 101 status = "disabled"; 102 103 counter { 104 compatible = "st,stm32-counter"; 105 status = "disabled"; 106 }; 107 }; 108 109 timers8: timers@40010400 { 110 compatible = "st,stm32-timers"; 111 reg = <0x40010400 0x400>; 112 clocks = <&rcc STM32_CLOCK(APB2, 1U)>; 113 resets = <&rctl STM32_RESET(APB2, 1U)>; 114 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 115 interrupt-names = "brk", "up", "trgcom", "cc"; 116 st,prescaler = <0>; 117 status = "disabled"; 118 119 pwm { 120 compatible = "st,stm32-pwm"; 121 status = "disabled"; 122 #pwm-cells = <3>; 123 }; 124 125 qdec { 126 compatible = "st,stm32-qdec"; 127 status = "disabled"; 128 st,input-filter-level = <NO_FILTER>; 129 }; 130 }; 131 132 timers12: timers@40001800 { 133 compatible = "st,stm32-timers"; 134 reg = <0x40001800 0x400>; 135 clocks = <&rcc STM32_CLOCK(APB1, 6U)>; 136 resets = <&rctl STM32_RESET(APB1, 6U)>; 137 interrupts = <43 0>; 138 interrupt-names = "global"; 139 st,prescaler = <0>; 140 status = "disabled"; 141 142 pwm { 143 compatible = "st,stm32-pwm"; 144 status = "disabled"; 145 #pwm-cells = <3>; 146 }; 147 148 counter { 149 compatible = "st,stm32-counter"; 150 status = "disabled"; 151 }; 152 }; 153 154 timers13: timers@40001c00 { 155 compatible = "st,stm32-timers"; 156 reg = <0x40001c00 0x400>; 157 clocks = <&rcc STM32_CLOCK(APB1, 7U)>; 158 resets = <&rctl STM32_RESET(APB1, 7U)>; 159 interrupts = <44 0>; 160 interrupt-names = "global"; 161 st,prescaler = <0>; 162 status = "disabled"; 163 164 pwm { 165 compatible = "st,stm32-pwm"; 166 status = "disabled"; 167 #pwm-cells = <3>; 168 }; 169 170 counter { 171 compatible = "st,stm32-counter"; 172 status = "disabled"; 173 }; 174 }; 175 176 timers14: timers@40002000 { 177 compatible = "st,stm32-timers"; 178 reg = <0x40002000 0x400>; 179 clocks = <&rcc STM32_CLOCK(APB1, 8U)>; 180 resets = <&rctl STM32_RESET(APB1, 8U)>; 181 interrupts = <45 0>; 182 interrupt-names = "global"; 183 st,prescaler = <0>; 184 status = "disabled"; 185 186 pwm { 187 compatible = "st,stm32-pwm"; 188 status = "disabled"; 189 #pwm-cells = <3>; 190 }; 191 192 counter { 193 compatible = "st,stm32-counter"; 194 status = "disabled"; 195 }; 196 }; 197 198 rng: rng@50060800 { 199 compatible = "st,stm32-rng"; 200 reg = <0x50060800 0x400>; 201 interrupts = <80 0>; 202 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 203 status = "disabled"; 204 }; 205 206 usbotg_fs: usb@50000000 { 207 num-bidir-endpoints = <6>; 208 }; 209 210 sdmmc1: sdmmc@40012c00 { 211 clocks = <&rcc STM32_CLOCK(APB2, 11U)>, 212 <&rcc STM32_SRC_CK48 SDIO_SEL(0)>; 213 }; 214 215 quadspi: quadspi@a0001000 { 216 compatible = "st,stm32-qspi"; 217 #address-cells = <0x1>; 218 #size-cells = <0x0>; 219 reg = <0xa0001000 0x400>; 220 interrupts = <92 0>; 221 clocks = <&rcc STM32_CLOCK(AHB3, 1U)>; 222 status = "disabled"; 223 }; 224 225 can1: can@40006400 { 226 compatible = "st,stm32-bxcan"; 227 reg = <0x40006400 0x400>; 228 interrupts = <19 0>, <20 0>, <21 0>, <22 0>; 229 interrupt-names = "TX", "RX0", "RX1", "SCE"; 230 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; 231 status = "disabled"; 232 }; 233 234 can2: can@40006800 { 235 compatible = "st,stm32-bxcan"; 236 reg = <0x40006800 0x400>; 237 interrupts = <63 0>, <64 0>, <65 0>, <66 0>; 238 interrupt-names = "TX", "RX0", "RX1", "SCE"; 239 /* also enabling clock for can1 (master instance) */ 240 clocks = <&rcc STM32_CLOCK(APB1, 26U)>; 241 master-can-reg = <0x40006400>; 242 status = "disabled"; 243 }; 244 }; 245 246 die_temp: dietemp { 247 io-channels = <&adc1 18>; 248 }; 249}; 250
