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/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_02/
Dpsoc6_02.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_01/
Dpsoc6_01.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40250000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-latest/tests/bsim/bluetooth/host/att/long_read/
Dbs_sync.c2 * SPDX-License-Identifier: Apache-2.0
55 void bs_bc_receive_msg_sync(uint ch, size_t size, uint8_t *data) in bs_bc_receive_msg_sync() argument
57 while (bs_bc_is_msg_received(ch) < size) { in bs_bc_receive_msg_sync()
60 bs_bc_receive_msg(ch, data, size); in bs_bc_receive_msg_sync()
81 static uint64_t counter; in bt_testlib_bs_sync_all() local
83 LOG_DBG("%llu d%u enter", counter, get_device_nbr()); in bt_testlib_bs_sync_all()
91 __ASSERT(counter_cfm == counter, "%luu %luu", counter_cfm, counter); in bt_testlib_bs_sync_all()
94 bs_bc_send_uint(backchannels[i], counter); in bt_testlib_bs_sync_all()
99 bs_bc_send_uint(backchannels[0], counter); in bt_testlib_bs_sync_all()
101 __ASSERT(counter_cfm == counter, "%luu %luu", counter_cfm, counter); in bt_testlib_bs_sync_all()
[all …]
/Zephyr-latest/tests/bsim/bluetooth/host/att/open_close/src/
Dbs_sync.c2 * SPDX-License-Identifier: Apache-2.0
55 void bs_bc_receive_msg_sync(uint ch, size_t size, uint8_t *data) in bs_bc_receive_msg_sync() argument
57 while (bs_bc_is_msg_received(ch) < size) { in bs_bc_receive_msg_sync()
60 bs_bc_receive_msg(ch, data, size); in bs_bc_receive_msg_sync()
81 static uint64_t counter; in bt_testlib_bs_sync_all() local
83 LOG_DBG("%llu d%u enter", counter, get_device_nbr()); in bt_testlib_bs_sync_all()
91 __ASSERT(counter_cfm == counter, "%luu %luu", counter_cfm, counter); in bt_testlib_bs_sync_all()
94 bs_bc_send_uint(backchannels[i], counter); in bt_testlib_bs_sync_all()
99 bs_bc_send_uint(backchannels[0], counter); in bt_testlib_bs_sync_all()
101 __ASSERT(counter_cfm == counter, "%luu %luu", counter_cfm, counter); in bt_testlib_bs_sync_all()
[all …]
/Zephyr-latest/drivers/watchdog/
DKconfig.nxp_fs262 # SPDX-License-Identifier: Apache-2.0
23 int "Watchdog error counter limit"
26 Sets the maximum value of the watchdog error counter. Each time a
27 watchdog failure occurs, the device increments this counter by 2. The
28 watchdog error counter is decremented by 1 each time the watchdog is
34 int "Watchdog refresh counter limit"
37 Sets the maximum value of the watchdog refresh counter. Each time the
38 watchdog is properly refreshed, this counter is incremented by 1. Each
39 time this counter reaches its maximum value and if the next refresh is
40 also good, the fault error counter is decremented by 1. Each time
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
[all …]
Dambiq_apollo3p_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/sensor/
Despressif,esp32-pcnt.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Espressif's Pulse Counter Mode (PCNT) controller Node
8 The pulse counter module is designed to count the number of
14 Each pulse counter unit has a 16-bit signed counter register.
17 to either increment or decrement the counter.
23 Each pulse counter unit also features a filter on each of the four inputs,
29 Example: Use PCNT to read a rotary-enconder
38 bias-pull-up;
43 Note: Check espressif,esp32-pinctrl.yaml for complete documentation regarding pinctrl.
48 pinctrl-0 = <&pcnt_default>;
[all …]
/Zephyr-latest/dts/arm/st/l0/
Dstm32l071.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l071", "st,stm32l0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-i2c-v2";
25 clock-frequency = <I2C_BITRATE_STANDARD>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/adi/max32/
Dmax32xxx.dtsi2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/adi_max32_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &flc0;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4f";
[all …]
Dmax32672.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32672_dma.h>
16 clock-frequency = <DT_FREQ_K(80)>;
23 /delete-node/ &clk_iso;
26 compatible = "adi,max32-adc-sar", "adi,max32-adc";
27 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
28 clock-divider = <16>;
29 channel-count = <16>;
30 track-count = <4>;
[all …]
Dmax32670.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32670_dma.h>
20 clock-frequency = <DT_FREQ_K(80)>;
27 compatible = "mmio-sram";
32 compatible = "mmio-sram";
37 compatible = "mmio-sram";
42 compatible = "mmio-sram";
47 compatible = "mmio-sram";
52 compatible = "mmio-sram";
[all …]
Dmax32690.dtsi2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32690_dma.h>
12 clock-frequency = <DT_FREQ_M(120)>;
21 erase-block-size = <16384>;
29 compatible = "adi,max32-gpio";
30 gpio-controller;
31 #gpio-cells = <2>;
39 compatible = "adi,max32-gpio";
[all …]
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
10 #include <zephyr/dt-bindings/flash_controller/xspi.h>
17 #clock-cells = <0>;
18 compatible = "st,stm32u5-pll-clock";
24 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
26 pinctrl: pin-controller@42020000 {
28 compatible = "st,stm32-gpio";
29 gpio-controller;
30 #gpio-cells = <2>;
[all …]
/Zephyr-latest/drivers/display/
DKconfig.mcux_elcdif1 # Copyright 2019,2023-2024 NXP
3 # SPDX-License-Identifier: Apache-2.0
27 a buffer equal in size to the connected panel.
37 int "Framebuffer size required by the eLCDIF driver"
41 The framebuffer size is computed as : panel_width * panel_height * bpp.
43 4-bytes pixel format, e.g. ARGB8888. Applications should change this value
44 according to the actual used resolution and format to optimize the heap size.
54 display_write is called with a framebuffer equal in size to the
66 display_write MUST supply a framebuffer equal in size to screen width
81 Rotate display counter-clockwise by 90 degrees.
[all …]
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f7_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f3.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f3_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
[all …]
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4p5.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &quadspi;
26 clk_hsi48: clk-hsi48 {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <DT_FREQ_M(48)>;
35 compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
38 flash-controller@40022000 {
40 erase-block-size = <4096>;
[all …]
Dstm32l471.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l471", "st,stm32l4", "simple-bus";
13 pinctrl: pin-controller@48000000 {
16 compatible = "st,stm32-gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
32 compatible = "st,stm32-gpio";
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f412.dtsi2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f411-plli2s-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32-clock-mux";
29 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
31 pinctrl: pin-controller@40020000 {
[all …]
/Zephyr-latest/dts/arm/st/h7rs/
Dstm32h7rs.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
13 #include <zephyr/dt-bindings/reset/stm32h7rs_reset.h>
14 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 tcc-0 = &tcc0;
13 tcc-1 = &tcc1;
14 tcc-2 = &tcc2;
19 compatible = "atmel,sam0-tcc";
23 clock-names = "GCLK", "MCLK";
27 counter-size = <24>;
31 compatible = "atmel,sam0-tcc";
35 clock-names = "GCLK", "MCLK";
39 counter-size = <24>;
[all …]
/Zephyr-latest/dts/bindings/pwm/
Datmel,sam0-tcc-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-tcc-pwm"
9 - name: base.yaml
10 - name: pwm-controller.yaml
11 - name: pinctrl-device.yaml
23 clock-names:
31 - 2
32 - 3
33 - 4
34 - 6
[all …]
Datmel,sam0-tc-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-tc-pwm"
9 - name: base.yaml
10 - name: pwm-controller.yaml
11 - name: pinctrl-device.yaml
23 clock-names:
31 - 2
33 counter-size:
36 description: Width of the TC counter in bits
38 - 8
[all …]

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