1/* 2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-m0+"; 18 reg = <0>; 19 }; 20 cpu@1 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-m4f"; 23 reg = <1>; 24 }; 25 }; 26 27 flash-controller@40250000 { 28 compatible = "infineon,cat1-flash-controller"; 29 reg = < 0x40250000 0x10000 >; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 flash0: flash@10000000 { 34 compatible = "soc-nv-flash"; 35 reg = <0x10000000 0x100000>; 36 write-block-size = <512>; 37 erase-block-size = <512>; 38 }; 39 flash1: flash@14000000 { 40 compatible = "soc-nv-flash"; 41 reg = <0x14000000 0x8000>; 42 write-block-size = <512>; 43 erase-block-size = <512>; 44 }; 45 }; 46 47 sram0: memory@8000000 { 48 compatible = "mmio-sram"; 49 reg = <0x8000000 0x48000>; 50 }; 51 52 soc { 53 pinctrl: pinctrl@40310000 { 54 compatible = "infineon,cat1-pinctrl"; 55 reg = <0x40310000 0x20000>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 }; 59 60 hsiom: hsiom@40310000 { 61 compatible = "infineon,cat1-hsiom"; 62 reg = <0x40310000 0x4000>; 63 interrupts = <15 6>, <16 6>; 64 status = "disabled"; 65 }; 66 67 gpio_prt0: gpio@40320000 { 68 compatible = "infineon,cat1-gpio"; 69 reg = <0x40320000 0x80>; 70 interrupts = <0 6>; 71 gpio-controller; 72 ngpios = <6>; 73 status = "disabled"; 74 #gpio-cells = <2>; 75 }; 76 gpio_prt1: gpio@40320080 { 77 compatible = "infineon,cat1-gpio"; 78 reg = <0x40320080 0x80>; 79 interrupts = <1 6>; 80 gpio-controller; 81 ngpios = <6>; 82 status = "disabled"; 83 #gpio-cells = <2>; 84 }; 85 gpio_prt2: gpio@40320100 { 86 compatible = "infineon,cat1-gpio"; 87 reg = <0x40320100 0x80>; 88 interrupts = <2 6>; 89 gpio-controller; 90 ngpios = <8>; 91 status = "disabled"; 92 #gpio-cells = <2>; 93 }; 94 gpio_prt3: gpio@40320180 { 95 compatible = "infineon,cat1-gpio"; 96 reg = <0x40320180 0x80>; 97 interrupts = <3 6>; 98 gpio-controller; 99 ngpios = <6>; 100 status = "disabled"; 101 #gpio-cells = <2>; 102 }; 103 gpio_prt4: gpio@40320200 { 104 compatible = "infineon,cat1-gpio"; 105 reg = <0x40320200 0x80>; 106 interrupts = <4 6>; 107 gpio-controller; 108 ngpios = <2>; 109 status = "disabled"; 110 #gpio-cells = <2>; 111 }; 112 gpio_prt5: gpio@40320280 { 113 compatible = "infineon,cat1-gpio"; 114 reg = <0x40320280 0x80>; 115 interrupts = <5 6>; 116 gpio-controller; 117 ngpios = <8>; 118 status = "disabled"; 119 #gpio-cells = <2>; 120 }; 121 gpio_prt6: gpio@40320300 { 122 compatible = "infineon,cat1-gpio"; 123 reg = <0x40320300 0x80>; 124 interrupts = <6 6>; 125 gpio-controller; 126 ngpios = <8>; 127 status = "disabled"; 128 #gpio-cells = <2>; 129 }; 130 gpio_prt7: gpio@40320380 { 131 compatible = "infineon,cat1-gpio"; 132 reg = <0x40320380 0x80>; 133 interrupts = <7 6>; 134 gpio-controller; 135 ngpios = <8>; 136 status = "disabled"; 137 #gpio-cells = <2>; 138 }; 139 gpio_prt8: gpio@40320400 { 140 compatible = "infineon,cat1-gpio"; 141 reg = <0x40320400 0x80>; 142 interrupts = <8 6>; 143 gpio-controller; 144 ngpios = <8>; 145 status = "disabled"; 146 #gpio-cells = <2>; 147 }; 148 gpio_prt9: gpio@40320480 { 149 compatible = "infineon,cat1-gpio"; 150 reg = <0x40320480 0x80>; 151 interrupts = <9 6>; 152 gpio-controller; 153 ngpios = <8>; 154 status = "disabled"; 155 #gpio-cells = <2>; 156 }; 157 gpio_prt10: gpio@40320500 { 158 compatible = "infineon,cat1-gpio"; 159 reg = <0x40320500 0x80>; 160 interrupts = <10 6>; 161 gpio-controller; 162 ngpios = <8>; 163 status = "disabled"; 164 #gpio-cells = <2>; 165 }; 166 gpio_prt11: gpio@40320580 { 167 compatible = "infineon,cat1-gpio"; 168 reg = <0x40320580 0x80>; 169 interrupts = <11 6>; 170 gpio-controller; 171 ngpios = <8>; 172 status = "disabled"; 173 #gpio-cells = <2>; 174 }; 175 gpio_prt12: gpio@40320600 { 176 compatible = "infineon,cat1-gpio"; 177 reg = <0x40320600 0x80>; 178 interrupts = <12 6>; 179 gpio-controller; 180 ngpios = <8>; 181 status = "disabled"; 182 #gpio-cells = <2>; 183 }; 184 gpio_prt13: gpio@40320680 { 185 compatible = "infineon,cat1-gpio"; 186 reg = <0x40320680 0x80>; 187 interrupts = <13 6>; 188 gpio-controller; 189 ngpios = <8>; 190 status = "disabled"; 191 #gpio-cells = <2>; 192 }; 193 gpio_prt14: gpio@40320700 { 194 compatible = "infineon,cat1-gpio"; 195 reg = <0x40320700 0x80>; 196 interrupts = <14 6>; 197 gpio-controller; 198 ngpios = <2>; 199 status = "disabled"; 200 #gpio-cells = <2>; 201 }; 202 203 uid: device_uid@16000600 { 204 compatible = "infineon,cat1-uid"; 205 reg = <0x16000600 0xb>; 206 status = "disabled"; 207 }; 208 209 adc0: adc@411d0000 { 210 compatible = "infineon,cat1-adc"; 211 reg = <0x411d0000 0x10000>; 212 interrupts = <138 6>; 213 status = "disabled"; 214 #io-channel-cells = <1>; 215 }; 216 217 scb0: scb@40610000 { 218 compatible = "infineon,cat1-scb"; 219 reg = <0x40610000 0x10000>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 interrupts = <41 6>; 223 status = "disabled"; 224 }; 225 scb1: scb@40620000 { 226 compatible = "infineon,cat1-scb"; 227 reg = <0x40620000 0x10000>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <42 6>; 231 status = "disabled"; 232 }; 233 scb2: scb@40630000 { 234 compatible = "infineon,cat1-scb"; 235 reg = <0x40630000 0x10000>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 interrupts = <43 6>; 239 status = "disabled"; 240 }; 241 scb3: scb@40640000 { 242 compatible = "infineon,cat1-scb"; 243 reg = <0x40640000 0x10000>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 interrupts = <44 6>; 247 status = "disabled"; 248 }; 249 scb4: scb@40650000 { 250 compatible = "infineon,cat1-scb"; 251 reg = <0x40650000 0x10000>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 interrupts = <45 6>; 255 status = "disabled"; 256 }; 257 scb5: scb@40660000 { 258 compatible = "infineon,cat1-scb"; 259 reg = <0x40660000 0x10000>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 interrupts = <46 6>; 263 status = "disabled"; 264 }; 265 scb6: scb@40670000 { 266 compatible = "infineon,cat1-scb"; 267 reg = <0x40670000 0x10000>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 interrupts = <47 6>; 271 status = "disabled"; 272 }; 273 scb7: scb@40680000 { 274 compatible = "infineon,cat1-scb"; 275 reg = <0x40680000 0x10000>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 interrupts = <48 6>; 279 status = "disabled"; 280 }; 281 scb8: scb@40690000 { 282 compatible = "infineon,cat1-scb"; 283 reg = <0x40690000 0x10000>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 interrupts = <18 6>; 287 status = "disabled"; 288 }; 289 290 timer0: timer@40260200 { 291 compatible = "infineon,cat1-timer"; 292 reg = <0x40260200 0x40>; 293 interrupts = <19 6>; 294 status = "disabled"; 295 }; 296 timer1: timer@40260240 { 297 compatible = "infineon,cat1-timer"; 298 reg = <0x40260240 0x40>; 299 interrupts = <20 6>; 300 status = "disabled"; 301 }; 302 303 watchdog0: watchdog@40260180 { 304 compatible = "infineon,cat1-watchdog"; 305 reg = <0x40260180 0xc>; 306 interrupts = <22 6>; 307 status = "disabled"; 308 }; 309 310 bluetooth: bless { 311 compatible = "infineon,cat1-bless-hci"; 312 interrupts = <24 1>; 313 status = "disabled"; 314 }; 315 316 counter0_0: counter@40380100 { 317 compatible = "infineon,cat1-counter"; 318 reg = <0x40380100 0x40>; 319 interrupts = <90 6>; 320 resolution = <32>; 321 status = "disabled"; 322 }; 323 counter0_1: counter@40380140 { 324 compatible = "infineon,cat1-counter"; 325 reg = <0x40380140 0x40>; 326 interrupts = <91 6>; 327 resolution = <32>; 328 status = "disabled"; 329 }; 330 counter0_2: counter@40380180 { 331 compatible = "infineon,cat1-counter"; 332 reg = <0x40380180 0x40>; 333 interrupts = <92 6>; 334 resolution = <32>; 335 status = "disabled"; 336 }; 337 counter0_3: counter@403801c0 { 338 compatible = "infineon,cat1-counter"; 339 reg = <0x403801c0 0x40>; 340 interrupts = <93 6>; 341 resolution = <32>; 342 status = "disabled"; 343 }; 344 counter0_4: counter@40380200 { 345 compatible = "infineon,cat1-counter"; 346 reg = <0x40380200 0x40>; 347 interrupts = <94 6>; 348 resolution = <32>; 349 status = "disabled"; 350 }; 351 counter0_5: counter@40380240 { 352 compatible = "infineon,cat1-counter"; 353 reg = <0x40380240 0x40>; 354 interrupts = <95 6>; 355 resolution = <32>; 356 status = "disabled"; 357 }; 358 counter0_6: counter@40380280 { 359 compatible = "infineon,cat1-counter"; 360 reg = <0x40380280 0x40>; 361 interrupts = <96 6>; 362 resolution = <32>; 363 status = "disabled"; 364 }; 365 counter0_7: counter@403802c0 { 366 compatible = "infineon,cat1-counter"; 367 reg = <0x403802c0 0x40>; 368 interrupts = <97 6>; 369 resolution = <32>; 370 status = "disabled"; 371 }; 372 counter1_0: counter@40390100 { 373 compatible = "infineon,cat1-counter"; 374 reg = <0x40390100 0x40>; 375 interrupts = <98 6>; 376 resolution = <16>; 377 status = "disabled"; 378 }; 379 counter1_1: counter@40390140 { 380 compatible = "infineon,cat1-counter"; 381 reg = <0x40390140 0x40>; 382 interrupts = <99 6>; 383 resolution = <16>; 384 status = "disabled"; 385 }; 386 counter1_2: counter@40390180 { 387 compatible = "infineon,cat1-counter"; 388 reg = <0x40390180 0x40>; 389 interrupts = <100 6>; 390 resolution = <16>; 391 status = "disabled"; 392 }; 393 counter1_3: counter@403901c0 { 394 compatible = "infineon,cat1-counter"; 395 reg = <0x403901c0 0x40>; 396 interrupts = <101 6>; 397 resolution = <16>; 398 status = "disabled"; 399 }; 400 counter1_4: counter@40390200 { 401 compatible = "infineon,cat1-counter"; 402 reg = <0x40390200 0x40>; 403 interrupts = <102 6>; 404 resolution = <16>; 405 status = "disabled"; 406 }; 407 counter1_5: counter@40390240 { 408 compatible = "infineon,cat1-counter"; 409 reg = <0x40390240 0x40>; 410 interrupts = <103 6>; 411 resolution = <16>; 412 status = "disabled"; 413 }; 414 counter1_6: counter@40390280 { 415 compatible = "infineon,cat1-counter"; 416 reg = <0x40390280 0x40>; 417 interrupts = <104 6>; 418 resolution = <16>; 419 status = "disabled"; 420 }; 421 counter1_7: counter@403902c0 { 422 compatible = "infineon,cat1-counter"; 423 reg = <0x403902c0 0x40>; 424 interrupts = <105 6>; 425 resolution = <16>; 426 status = "disabled"; 427 }; 428 counter1_8: counter@40390300 { 429 compatible = "infineon,cat1-counter"; 430 reg = <0x40390300 0x40>; 431 interrupts = <106 6>; 432 resolution = <16>; 433 status = "disabled"; 434 }; 435 counter1_9: counter@40390340 { 436 compatible = "infineon,cat1-counter"; 437 reg = <0x40390340 0x40>; 438 interrupts = <107 6>; 439 resolution = <16>; 440 status = "disabled"; 441 }; 442 counter1_10: counter@40390380 { 443 compatible = "infineon,cat1-counter"; 444 reg = <0x40390380 0x40>; 445 interrupts = <108 6>; 446 resolution = <16>; 447 status = "disabled"; 448 }; 449 counter1_11: counter@403903c0 { 450 compatible = "infineon,cat1-counter"; 451 reg = <0x403903c0 0x40>; 452 interrupts = <109 6>; 453 resolution = <16>; 454 status = "disabled"; 455 }; 456 counter1_12: counter@40390400 { 457 compatible = "infineon,cat1-counter"; 458 reg = <0x40390400 0x40>; 459 interrupts = <110 6>; 460 resolution = <16>; 461 status = "disabled"; 462 }; 463 counter1_13: counter@40390440 { 464 compatible = "infineon,cat1-counter"; 465 reg = <0x40390440 0x40>; 466 interrupts = <111 6>; 467 resolution = <16>; 468 status = "disabled"; 469 }; 470 counter1_14: counter@40390480 { 471 compatible = "infineon,cat1-counter"; 472 reg = <0x40390480 0x40>; 473 interrupts = <112 6>; 474 resolution = <16>; 475 status = "disabled"; 476 }; 477 counter1_15: counter@403904c0 { 478 compatible = "infineon,cat1-counter"; 479 reg = <0x403904c0 0x40>; 480 interrupts = <113 6>; 481 resolution = <16>; 482 status = "disabled"; 483 }; 484 counter1_16: counter@40390500 { 485 compatible = "infineon,cat1-counter"; 486 reg = <0x40390500 0x40>; 487 interrupts = <114 6>; 488 resolution = <16>; 489 status = "disabled"; 490 }; 491 counter1_17: counter@40390540 { 492 compatible = "infineon,cat1-counter"; 493 reg = <0x40390540 0x40>; 494 interrupts = <115 6>; 495 resolution = <16>; 496 status = "disabled"; 497 }; 498 counter1_18: counter@40390580 { 499 compatible = "infineon,cat1-counter"; 500 reg = <0x40390580 0x40>; 501 interrupts = <116 6>; 502 resolution = <16>; 503 status = "disabled"; 504 }; 505 counter1_19: counter@403905c0 { 506 compatible = "infineon,cat1-counter"; 507 reg = <0x403905c0 0x40>; 508 interrupts = <117 6>; 509 resolution = <16>; 510 status = "disabled"; 511 }; 512 counter1_20: counter@40390600 { 513 compatible = "infineon,cat1-counter"; 514 reg = <0x40390600 0x40>; 515 interrupts = <118 6>; 516 resolution = <16>; 517 status = "disabled"; 518 }; 519 counter1_21: counter@40390640 { 520 compatible = "infineon,cat1-counter"; 521 reg = <0x40390640 0x40>; 522 interrupts = <119 6>; 523 resolution = <16>; 524 status = "disabled"; 525 }; 526 counter1_22: counter@40390680 { 527 compatible = "infineon,cat1-counter"; 528 reg = <0x40390680 0x40>; 529 interrupts = <120 6>; 530 resolution = <16>; 531 status = "disabled"; 532 }; 533 counter1_23: counter@403906c0 { 534 compatible = "infineon,cat1-counter"; 535 reg = <0x403906c0 0x40>; 536 interrupts = <121 6>; 537 resolution = <16>; 538 status = "disabled"; 539 }; 540 541 sdhc0: sdhc@40460000 { 542 compatible = "infineon,cat1-sdhc-sdio"; 543 reg = <0x40460000 0x2000>; 544 interrupts = <164 6>; 545 status = "disabled"; 546 }; 547 }; 548}; 549
