1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9#include <zephyr/dt-bindings/dma/max32670_dma.h>
10
11&sram0 {
12	reg = <0x20000000 DT_SIZE_K(16)>;
13};
14
15&flash0 {
16	reg = <0x10000000 DT_SIZE_K(384)>;
17};
18
19&clk_inro {
20	clock-frequency = <DT_FREQ_K(80)>;
21};
22
23/* MAX32670 extra peripherals. */
24/ {
25	soc {
26		sram1: memory@20004000 {
27			compatible = "mmio-sram";
28			reg = <0x20004000 DT_SIZE_K(16)>;
29		};
30
31		sram2: memory@20008000 {
32			compatible = "mmio-sram";
33			reg = <0x20008000 DT_SIZE_K(32)>;
34		};
35
36		sram3: memory@20010000 {
37			compatible = "mmio-sram";
38			reg = <0x20010000 DT_SIZE_K(64)>;
39		};
40
41		sram4: memory@20020000 {
42			compatible = "mmio-sram";
43			reg = <0x20020000 DT_SIZE_K(4)>;
44		};
45
46		sram5: memory@20021000 {
47			compatible = "mmio-sram";
48			reg = <0x20021000 DT_SIZE_K(4)>;
49		};
50
51		sram6: memory@20022000 {
52			compatible = "mmio-sram";
53			reg = <0x20022000 DT_SIZE_K(8)>;
54		};
55
56		sram7: memory@20024000 {
57			compatible = "mmio-sram";
58			reg = <0x20024000 DT_SIZE_K(16)>;
59		};
60
61		uart3: serial@40145000 {
62			compatible = "adi,max32-uart";
63			reg = <0x40145000 0x1000>;
64			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
65			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
66			interrupts = <88 0>;
67			status = "disabled";
68		};
69
70		dma0: dma@40028000 {
71			compatible = "adi,max32-dma";
72			reg = <0x40028000 0x1000>;
73			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
74			interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
75			dma-channels = <8>;
76			status = "disabled";
77			#dma-cells = <2>;
78		};
79
80		wdt1: watchdog@40003400  {
81			compatible = "adi,max32-watchdog";
82			reg = <0x40003400 0x400>;
83			interrupts = <57 0>;
84			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 5>;
85			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
86			status = "disabled";
87		};
88
89		spi0: spi@40046000 {
90			compatible = "adi,max32-spi";
91			reg = <0x40046000 0x1000>;
92			#address-cells = <1>;
93			#size-cells = <0>;
94			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
95			interrupts = <16 0>;
96			status = "disabled";
97		};
98
99		spi1: spi@40047000 {
100			compatible = "adi,max32-spi";
101			reg = <0x40047000 0x1000>;
102			#address-cells = <1>;
103			#size-cells = <0>;
104			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
105			interrupts = <17 0>;
106			status = "disabled";
107		};
108
109		spi2: spi@40048000 {
110			compatible = "adi,max32-spi";
111			reg = <0x40048000 0x1000>;
112			#address-cells = <1>;
113			#size-cells = <0>;
114			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
115			interrupts = <18 0>;
116			status = "disabled";
117		};
118
119		lptimer0: timer@40114000 {
120			compatible = "adi,max32-timer";
121			reg = <0x40114000 0x1000>;
122			interrupts = <9 0>;
123			status = "disabled";
124			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
125			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
126			prescaler = <1>;
127			counter {
128				compatible = "adi,max32-counter";
129				status = "disabled";
130			};
131		};
132
133		lptimer1: timer@40115000 {
134			compatible = "adi,max32-timer";
135			reg = <0x40115000 0x1000>;
136			interrupts = <10 0>;
137			status = "disabled";
138			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
139			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
140			prescaler = <1>;
141			counter {
142				compatible = "adi,max32-counter";
143				status = "disabled";
144			};
145		};
146	};
147};
148